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Download or read book Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit HOL Listings written by David A. Fura and published by . This book was released on 1993 with total page 188 pages. Available in PDF, EPUB and Kindle. Book excerpt:
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Download or read book Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit written by National Aeronautics and Space Administration (NASA) and published by Createspace Independent Publishing Platform. This book was released on 2018-07-23 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port. Fura, David A. and Windley, Phillip J. and Cohen, Gerald C. Unspecified Center AIRBORNE/SPACEBORNE COMPUTERS; AVIONICS; CHIPS (ELECTRONICS); COMPUTER PROGRAMS; DESIGN ANALYSIS; FAULT TOLERANCE; LOGIC DESIGN; MICROPROCESSORS; PROVING; SOFTWARE RELIABILITY; SPECIFICATIONS...
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