Download or read book High Quality Compact Delay Test Generation written by Zheng Wang and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test.

Download or read book A Unified Approach for Timing Verification and Delay Fault Testing written by Mukund Sivaraman and published by Springer Science & Business Media. This book was released on 2012-09-17 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.

Download or read book Testing for Small Delay Defects in Nanoscale CMOS Integrated Circuits written by Sandeep K. Goel and published by CRC Press. This book was released on 2017-12-19 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.

Download or read book Testing of Digital Systems written by N. K. Jha and published by Cambridge University Press. This book was released on 2003-05-08 with total page 1022 pages. Available in PDF, EPUB and Kindle. Book excerpt: Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

Download or read book Design and Test Technology for Dependable Systems on chip written by Raimund Ubar and published by IGI Global. This book was released on 2011-01-01 with total page 550 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

Download or read book Delay Test Generation Techniques for Compact SDD Pattern Volume High SDD Coverage and Speed Binning written by Fang Bao and published by . This book was released on 2014 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book 19th IEEE VLSI Test Symposium written by and published by Institute of Electrical & Electronics Engineers(IEEE). This book was released on 2001 with total page 458 pages. Available in PDF, EPUB and Kindle. Book excerpt: Collects 58 papers from the April/May 2001 symposium that explore new approaches in the testing of electronic circuits and systems. Key areas in testing are discussed, such as BIST, analog measurement, fault tolerance, diagnosis methods, scan chain design, memory test and diagnosis, and test data compression and compaction. Also on the program are sessions on emerging areas that are gaining prominence, including low power testing, testing high speed circuits on low cost testers, processor based self test techniques, and core- based system-on-chip testing. Some of the topics are robust and low cost BIST architectures for sequential fault testing in datapath multipliers, a method for measuring the cycle-to-cycle period jitter of high-frequency clock signals, fault equivalence identification using redundancy information and static and dynamic extraction, and test scheduling for minimal energy consumption under power constraints. No subject index. c. Book News Inc.

Download or read book Nanometer Technology Designs written by Nisar Ahmed and published by Springer Science & Business Media. This book was released on 2010-02-26 with total page 288 pages. Available in PDF, EPUB and Kindle. Book excerpt: Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.

Download or read book Electronic Design Automation for IC System Design Verification and Testing written by Luciano Lavagno and published by CRC Press. This book was released on 2017-12-19 with total page 773 pages. Available in PDF, EPUB and Kindle. Book excerpt: The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.

Download or read book 16th IEEE VLSI Test Symposium written by and published by . This book was released on 1998 with total page 528 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Test Generation of Crosstalk Delay Faults in VLSI Circuits written by S. Jayanthy and published by Springer. This book was released on 2018-09-20 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

Download or read book Pseudofunctional Delay Tests for High Quality Small Delay Defect Testing written by Shayak Lahiri and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.

Download or read book Proceedings written by and published by . This book was released on 1999 with total page 428 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Advances in Electronic Testing written by Dimitris Gizopoulos and published by Springer Science & Business Media. This book was released on 2006-01-22 with total page 431 pages. Available in PDF, EPUB and Kindle. Book excerpt: This is a new type of edited volume in the Frontiers in Electronic Testing book series devoted to recent advances in electronic circuits testing. The book is a comprehensive elaboration on important topics which capture major research and development efforts today. "Hot" topics of current interest to test technology community have been selected, and the authors are key contributors in the corresponding topics.

Download or read book New Trends in Computational Vision and Bio inspired Computing written by S. Smys and published by Springer Nature. This book was released on 2020-09-27 with total page 1664 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume gathers selected, peer-reviewed original contributions presented at the International Conference on Computational Vision and Bio-inspired Computing (ICCVBIC) conference which was held in Coimbatore, India, on November 29-30, 2018. The works included here offer a rich and diverse sampling of recent developments in the fields of Computational Vision, Fuzzy, Image Processing and Bio-inspired Computing. The topics covered include computer vision; cryptography and digital privacy; machine learning and artificial neural networks; genetic algorithms and computational intelligence; the Internet of Things; and biometric systems, to name but a few. The applications discussed range from security, healthcare and epidemic control to urban computing, agriculture and robotics. In this book, researchers, graduate students and professionals will find innovative solutions to real-world problems in industry and society as a whole, together with inspirations for further research.

Download or read book Optical Communication with Chaotic Lasers written by Atsushi Uchida and published by John Wiley & Sons. This book was released on 2012-02-13 with total page 669 pages. Available in PDF, EPUB and Kindle. Book excerpt: Starting with an introduction to the fundamental physics in chaotic instabilities in laser systems, this comprehensive and unified reference goes on to present the techniques and technology of synchronization of chaos in coupled lasers, as well as the many applications to lasers and optics, communications, security and information technology. Throughout, it presents the current state of knowledge, including encoding/decoding techniques, performance of chaotic communication systems, random number generation, and novel communication technologies.

Download or read book Enterprise Network Testing written by Andy Sholomon and published by Pearson Education. This book was released on 2011-04-14 with total page 730 pages. Available in PDF, EPUB and Kindle. Book excerpt: Enterprise Network Testing Testing Throughout the Network Lifecycle to Maximize Availability and Performance Andy Sholomon, CCIE® No. 15179 Tom Kunath, CCIE No. 1679 The complete guide to using testing to reduce risk and downtime in advanced enterprise networks Testing has become crucial to meeting enterprise expectations of near-zero network downtime. Enterprise Network Testing is the first comprehensive guide to all facets of enterprise network testing. Cisco enterprise consultants Andy Sholomon and Tom Kunath offer a complete blueprint and best-practice methodologies for testing any new network system, product, solution, or advanced technology. Sholomon and Kunath begin by explaining why it is important to test and how network professionals can leverage structured system testing to meet specific business goals. Then, drawing on their extensive experience with enterprise clients, they present several detailed case studies. Through real-world examples, you learn how to test architectural “proofs of concept,” specific network features, network readiness for use, migration processes, security, and more. Enterprise Network Testing contains easy-to-adapt reference test plans for branches, WANs/MANs, data centers, and campuses. The authors also offer specific guidance on testing many key network technologies, including MPLS/VPN, QoS, VoIP, video, IPsec VPNs, advanced routing (OSPF, EIGRP, BGP), and Data Center Fabrics. § Understand why, when, and how you should test your network § Use testing to discover critical network design flaws § Incorporate structured systems testing into enterprise architecture strategy § Utilize testing to improve decision-making throughout the network lifecycle § Develop an effective testing organization and lab facility § Choose and use test services providers § Scope, plan, and manage network test assignments § nLeverage the best commercial, free, and IOS test tools § Successfully execute test plans, including crucial low-level details § Minimize the equipment required to test large-scale networks § Identify gaps in network readiness § Validate and refine device configurations § Certify new hardware, operating systems, and software features § Test data center performance and scalability § Leverage test labs for hands-on technology training This book is part of the Networking Technology Series from Cisco Press®, which offers networking professionals valuable information for constructing efficient networks, understanding new technologies, and building successful careers.