Download or read book An Optimized Implementation of a Fault Tolerant Clock Synchronization Circuit written by National Aeronautics and Space Administration (NASA) and published by Createspace Independent Publishing Platform. This book was released on 2018-06-30 with total page 28 pages. Available in PDF, EPUB and Kindle. Book excerpt: A fault-tolerant clock synchronization circuit was designed and tested. A comparison to a previous design and the procedure followed to achieve the current optimization are included. The report also includes a description of the system and the results of tests performed to study the synchronization and fault-tolerant characteristics of the implementation. Torres-Pomales, Wilfredo Langley Research Center RTOP 505-64-10-13...
Download or read book An Optimized Implementation of a Fault tolerant Clock Synchronization Circuit written by and published by . This book was released on 1995 with total page 30 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Verified Design of a Fault Tolerant Clock Synchronization Circuit written by National Aeronautics and Space Administration (NASA) and published by Createspace Independent Publishing Platform. This book was released on 2018-07-17 with total page 104 pages. Available in PDF, EPUB and Kindle. Book excerpt: Schneider demonstrates that many fault tolerant clock synchronization algorithms can be represented as refinements of a single proven correct paradigm. Shankar provides mechanical proof that Schneider's schema achieves Byzantine fault tolerant clock synchronization provided that 11 constraints are satisfied. Some of the constraints are assumptions about physical properties of the system and cannot be established formally. Proofs are given that the fault tolerant midpoint convergence function satisfies three of the constraints. A hardware design is presented, implementing the fault tolerant midpoint function, which is shown to satisfy the remaining constraints. The synchronization circuit will recover completely from transient faults provided the maximum fault assumption is not violated. The initialization protocol for the circuit also provides a recovery mechanism from total system failure caused by correlated transient faults. Miner, Paul S. Langley Research Center ALGORITHMS; CIRCUITS; CLOCKS; FAULT TOLERANCE; SYNCHRONISM; CONVERGENCE; PROTOCOL (COMPUTERS); PROVING; SYSTEM FAILURES...
Download or read book A Hardware Implementation of a Provably Correct Design of a Fault tolerant Clock Synchronization Circuit written by and published by . This book was released on 1993 with total page 18 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Hardware Implementation of a Probably Correct Design of a Fault tolerant Clock Synchronization Circuit written by Wilfredo Torres-Pomales and published by . This book was released on 1993 with total page 11 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Hardware Implementation of a Provably Correct Design of a Fault Tolerant Clock Synchronization Circuit written by National Aeronautics and Space Administration (NASA) and published by Createspace Independent Publishing Platform. This book was released on 2018-08-09 with total page 32 pages. Available in PDF, EPUB and Kindle. Book excerpt: A fault-tolerant clock synchronization system was designed to a proven correct formal specification. Formal methods were used in the development of this specification. A description of the system and an analysis of the tests performed are presented. Plots of typical experimental results are included. Torres-Pomales, Wilfredo Langley Research Center NASA-TM-109001, NAS 1.15:109001 RTOP 505-64-10-10...
Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1995 with total page 702 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book An Extension to Schneider s General Paradigm for Fault tolerant Clock Synchronization written by Paul S. Miner and published by . This book was released on 1992 with total page 60 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Verified Design of a Fault tolerant Clock Synchronization Circuit Preliminary Investigations written by and published by . This book was released on 1992 with total page 106 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Third NASA Langley Formal Methods Workshop written by and published by . This book was released on 1995 with total page 274 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Monthly Catalogue United States Public Documents written by and published by . This book was released on 1995 with total page 1484 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Monthly Catalog of United States Government Publications written by and published by . This book was released on 1994 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Formal Methods in Computer Aided Design written by Mandayam Srivas and published by Springer Science & Business Media. This book was released on 1996-10-23 with total page 490 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the First International Conference on Formal Methods in Computer-Aided Design, FMCAD '96, held in Palo Alto, California, USA, in November 1996. The 25 revised full papers presented were selected from a total of 65 submissions; also included are three invited survey papers and four tutorial contributions. The volume covers all relevant formal aspects of work in computer-aided systems design, including verification, synthesis, and testing.
Download or read book Theorem Proving in Higher Order Logics written by Yves Bertot and published by Springer. This book was released on 2003-07-31 with total page 363 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics, TPHOLs '99, held in Nice, France, in September 1999. The 20 revised full papers presented together with three invited contributions were carefully reviewed and selected from 35 papers submitted. All current aspects of higher order theorem proving, formal verification, and specification are discussed. Among the theorem provers evaluated are COQ, HOL, Isabelle, Isabelle/ZF, and OpenMath.
Download or read book Government Reports Announcements Index written by and published by . This book was released on 1995 with total page 802 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Integrated Circuit and System Design Power and Timing Modeling Optimization and Simulation written by José L. Ayala and published by Springer. This book was released on 2013-01-03 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Download or read book Integrated Circuit and System Design Power and Timing Modeling Optimization and Simulation written by Vassilis Paliouras and published by Springer Science & Business Media. This book was released on 2005-09-06 with total page 767 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-power processors, code optimization for low-power, high-level design, telecommunications and signal processing, low-power circuits, system-on-chip design, busses and interconnections, modeling, design automation, low-power techniques, memory and register files, applications, digital circuits, and analog and physical design.
