Download or read book Switch level Fault Simulation of MOS VLSI Circuits written by Evstratios Vandris and published by . This book was released on 1991 with total page 304 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Symbolic Switch level Logic and Fault Simulation of MOS VLSI Circuit written by Daniel Georges Saab and published by . This book was released on 1985 with total page 122 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Switch Level Timing Simulation of MOS VLSI Circuits written by Vasant B. Rao and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 218 pages. Available in PDF, EPUB and Kindle. Book excerpt: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

Download or read book Switch level Fault Simulation of MOS Digital Circuits written by Michael D. Schuster and published by . This book was released on 1984 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Switch level Concurrent Fault Simulator for MOS Circuits written by Terry Ping-Chung Lee and published by . This book was released on 1991 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Advanced Simulation and Test Methodologies for VLSI Design written by G. Russell and published by Springer Science & Business Media. This book was released on 1989-02-28 with total page 406 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Switch level Timing Simulation of MOS VLSI Circuits written by Vasant Bangalore Rao and published by . This book was released on 1985 with total page 476 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report deals with the development of a fast and accurate simulation tool for very-large-scale integrated (VLSI) circuits consisting of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented in this thesis can handle only n-channel MOS(NMOS) circuits, but are easily extendible to handle complementary MOS(CMOS) circuits as well. The algorithms presented in this report have been implemented in a computer program called MOSTIM. In all the circuits simulated thus far, MOSTIM provides timing information with an accuracy of within 10% of that provided by SPICE2, at approximately two orders of magnitude faster in simulation speed. (Author).

Download or read book VLSI Fault Modeling and Testing Techniques written by George W. Zobrist and published by Praeger. This book was released on 1993 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.

Download or read book IDDQ Testing of VLSI Circuits written by Ravi K. Gulati and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 121 pages. Available in PDF, EPUB and Kindle. Book excerpt: Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.

Download or read book Fault Simulation and Transistor level Test Generation for Physical Failures in MOS Circuits written by Hsi-Ching Shih and published by . This book was released on 1986 with total page 202 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Download or read book Tutorial Test Generation for VLSI Circuits written by Sharad C. Seth and published by . This book was released on 1987 with total page 102 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fault Simulation and Transisto level Test generation for Physical Failures in MOS Circuits written by Hsi-Ching Shih and published by . This book was released on 1987 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Hot Carrier Reliability of MOS VLSI Circuits written by Yusuf Leblebici and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 223 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.

Download or read book LSI VLSI Testability Design written by Frank F. Tsui and published by McGraw-Hill Companies. This book was released on 1987 with total page 730 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1995 with total page 702 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book VLSI and Computer Architecture written by Ravi Shankar and published by Academic Press. This book was released on 2014-12-01 with total page 502 pages. Available in PDF, EPUB and Kindle. Book excerpt: VLSI Electronics Microstructure Science, Volume 20: VLSI and Computer Architecture reviews the approaches in design principles and techniques and the architecture for computer systems implemented in VLSI. This volume is divided into two parts. The first section is concerned with system design. Chapters under this section focus on the discussion of such topics as the evolution of VLSI; system performance and processor design considerations; and VLSI system design and processing tools. Part II of the book focuses on the architectural possibilities that have become cost effective with the development of VLSI circuits. Topics on architectural requirements and various architectures such as the Reduced Instruction Set, Extended Von Neumann, Language-Oriented, and Microprogrammable architectures are elaborated in detail. Also included are chapters that discuss the evaluation of architecture, multiprocessing configurations, and the future of VLSI. Computer designers, those evaluating computer systems, researchers, and students of computer architecture will find the book very useful.