Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume I Executive Summary written by M. A. Breuer and published by . This book was released on 1982 with total page 24 pages. Available in PDF, EPUB and Kindle. Book excerpt: This project is a two-phase study dealing with testing and testability of custom LSI/VLSI circuits. The tasks summarized and evaluated in this report consisted of compiling and documenting a survey and assessment of the state-of-the-art for each of seven topics. Each of these topics has resulted in a formal report and are listed below: Vol. 2: Hardware Design Verification; Vol. 3: Fault Mode Analysis; Vol. 4: Test Generation; Vol. 5: Design for Testability; Vol. 6: Redundancy, Testing Circuits, and Codes; Vol. 7: Built-in Testing (BIT) and Built-in Test Equipment (BITE); and Vol. 8: Fault Simulation.
Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1983 with total page 1252 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume V Design for Testability written by A. J. Carlan and published by . This book was released on 1982 with total page 68 pages. Available in PDF, EPUB and Kindle. Book excerpt: Designing for testability if needed to reduce costs associated with testing and maintaining electronic systems. Two approaches are considered: (1) modification of established circuits and (2) general design of new circuits where testability is a major consideration. Computer programs TMEAS and SCOAP, developed for evaluating testability in established circuits, are discussed. In the design of new circuits only a few techniques are known that yield highly testable circuits without sacrificing other desirable traits, two, IBM's LSSD method and bit slicing, are discussed. (Author).
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume III Fault Model Analysis written by M. A. Breuer and published by . This book was released on 1982 with total page 43 pages. Available in PDF, EPUB and Kindle. Book excerpt: Physical failure in LSI/VSLI circuits is highly dependent on the fabrication technology being used and result in a very complex faulty behavior. To reduce numbers and types of faults that must be handled for test generating and fault simulation, logic fault models are used. The most popular fault model is the single stuck line (SSL) which can emulate many common physical faults. Non-standard faults like short circuits are more difficult to model-usually require modification to the original circuit to allow use of SSL software. This approach is also ideal for handling Complementary Metal oxide Semiconductors faults. (Author).
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume IV Test Generation written by M. A. Breuer and published by . This book was released on 1982 with total page 67 pages. Available in PDF, EPUB and Kindle. Book excerpt: Two major approaches are considered for generating tests for digital systems: methods based on detailed circuit models of the unit under test (UUT) and methods based primarily on a functional description of the UUT. In addition to test generation of general digital systems, the testing requirements of microprocessors, semiconductor memories and PLA are examined. The D-algorithm and several variants are discussed as a basis for practical test generation procedures. (Author).
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume VII Built In Testing BIT and Built In Test Equipment BITE written by Al J. Carlan and published by . This book was released on 1982 with total page 42 pages. Available in PDF, EPUB and Kindle. Book excerpt: Concurrent testing and nonconcurrent testing are the two major BIT techniques employed in VSLI circuit design; concurrent testing and nonconcurrent testing. concurrent testing allows circuit checkout during normal system; and may employ error detecting codes, self checking circuits, replication or electrical monitoring. Nonconcurrent testing requires a special test mode during which normal system operation is halted. Circuits must be added to generate the test patterns used during test mode. Circuits must be added to generate the test patterns used during test mode. Nonconcurrent testing is initiated by hardware implemented BITE or diagnostic software. (Author).
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume II Hardware Design Verification written by A. J. Carlan and published by . This book was released on 1982 with total page 58 pages. Available in PDF, EPUB and Kindle. Book excerpt: The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume VI Redundancy Testing Circuits and Codes written by M. A. Breuer and published by . This book was released on 1982 with total page 92 pages. Available in PDF, EPUB and Kindle. Book excerpt: The demands for higher system reliability and self checking required by the new fault tolerant computers have put new emphais on the use of the redundant circuits. Types of redundancy include parallel, triple modular redundancy, Quadd, standby, hybrid and software. Various computers employing one or more of these types are discussed. Generally, hardware, software and time redundancy required for error detection and correltion, are interrelated. Mathematical modleing, when applied to fault tolerant systems, can be used to measure the system reliability.
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume VIII Fault Simulation written by M. A. Breuer and published by . This book was released on 1982 with total page 27 pages. Available in PDF, EPUB and Kindle. Book excerpt: Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy i.e. modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions etc, circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising. (Author).
Download or read book Government Reports Annual Index written by and published by . This book was released on 1983 with total page 1212 pages. Available in PDF, EPUB and Kindle. Book excerpt: Sections 1-2. Keyword Index.--Section 3. Personal author index.--Section 4. Corporate author index.-- Section 5. Contract/grant number index, NTIS order/report number index 1-E.--Section 6. NTIS order/report number index F-Z.
Download or read book Government Reports Annual Index Keyword A L written by and published by . This book was released on 1983 with total page 1216 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Interference Problems on Wing fuselage Combinations in Inviscid Incompressible Flow written by Aeronautical Research Council (Great Britain) and published by . This book was released on 1974 with total page 1212 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Electronic Engineering written by and published by . This book was released on 1984 with total page 1120 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Download or read book Contactless VLSI Measurement and Testing Techniques written by Selahattin Sayil and published by Springer. This book was released on 2017-11-16 with total page 92 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides readers with a comprehensive overview of the state-of-the-art in optical contactless probing approaches, in order to fill a gap in the literature on VLSI Testing. The author highlights the inherent difficulties encountered with the mechanical probe and testability design approaches for functional and internal fault testing and shows how contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. The techniques described in this book address the increasing demands for internal access of the logic state of a node within a chip under test.
Download or read book Government Reports Announcements Index written by and published by . This book was released on 1983 with total page 1600 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Analysis and Design of Resilient VLSI Circuits written by Rajesh Garg and published by Springer Science & Business Media. This book was released on 2009-10-22 with total page 224 pages. Available in PDF, EPUB and Kindle. Book excerpt: This monograph is motivated by the challenges faced in designing reliable VLSI systems in modern VLSI processes. The reliable operation of integrated circuits (ICs) has become increasingly dif?cult to achieve in the deep submicron (DSM) era. With continuouslydecreasing device feature sizes, combinedwith lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations, and radiation-inducedsoft errors. Among these noise sources, soft errors(or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as c- binational logic circuits. Also, in the DSM era, process variations are increasing at a signi?cant rate, making it more dif?cult to design reliable VLSI circuits. Hence, it is important to ef?ciently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this research mo- graph presents several analysis and design techniques with the goal of realizing VLSI circuits, which are radiation and process variation tolerant.
