Download or read book Multiple Faults in Combinational Logic written by H. G. Shah and published by . This book was released on 1973 with total page 72 pages. Available in PDF, EPUB and Kindle. Book excerpt: The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author).
Download or read book Fault Detection for Combinational Logic Under the Multiple Fault Assumption written by Patrick Wai-Fai Lam and published by . This book was released on 1971 with total page 92 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Adaptive Location of Multiple Faults in Combinational Circuits written by Alan Douglas May and published by . This book was released on 1984 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multiple Fault Analysis in Combinational Logic Circuits written by Francisco Jose de Oliveira Dias and published by . This book was released on 1975 with total page 364 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multiple Fault Detection in Combinational Circuits written by Sivanarayana Mallela and published by . This book was released on 1976 with total page 128 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test generation and fault diagnosis for multiple faults in combinational circuits written by Stanford University. Computer Systems Laboratory and published by . This book was released on 1983 with total page 52 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multiple Fault Diagnosis in Combinational Networks written by Charles Wei-Yuan Cha and published by . This book was released on 1974 with total page 114 pages. Available in PDF, EPUB and Kindle. Book excerpt: A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Download or read book Digital Circuit Testing and Testability written by Parag K. Lala and published by Academic Press. This book was released on 1997 with total page 222 pages. Available in PDF, EPUB and Kindle. Book excerpt: An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.
Download or read book Automated Multiple Fault Test Generation for Combinational Networks written by Robert A. Hendrix and published by . This book was released on 1976 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Download or read book Fault Analysis of Combinational Logic Networks written by Lung-Hsiung Chang and published by . This book was released on 1974 with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Fault Diagnosis of Multiple Output Combinational Logic Networks written by Heramb Singh and published by . This book was released on 1971 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book On Computing Test Vectors for Multiple Faults in Gate Level Combinational Circuits written by Sreejit Chakravarty and published by . This book was released on 1987 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multiple Fault Detection in Logic Circuits written by Shih-Chien Yang and published by . This book was released on 1973 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Testing for multiple intermittent failures in combinational circuits by maximizing the probability of fault detection written by Stanford University Stanford Electronics Laboratories. Digital Systems Laboratory and published by . This book was released on 1977 with total page 36 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multiple Fault Analysis in Synchronous Sequential Circuits by Means of Vector Boolean Difference written by and published by . This book was released on 1977 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is an elegant mathematical concept which has found significant application in the study of single faults of a stuck-at nature in combinational logic circuits. Recently, several authors have extended this technique to the analysis of multiple faults in combinational circuits. The concept of vector Boolean difference is further extended to the analysis of multiple stuck-at faults in synchronous sequential circuits.
Download or read book Analysis of Multiple Faults in Synchronous Sequential Circuits by Boolean Difference Techniques written by and published by . This book was released on 1978 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is a mathematical concept which has found significant application in the study of single and multiple ''stuck at'' faults in combinational logic circuits. The concept of vector Boolean difference is extended to the analysis of multiple stuck-at faults in synchronous sequential circuits. A vector Boolean difference technique is utilized to determine the set of input/state pairs that will produce a difference in either output or next-state between the fault-free and faulty circuits. Assuming that the fault-free and faulty circuits start in the same initial state, they must be driven by applying a sequence of input vectors to a state in which either a difference in output or next-state is evidenced. If a difference in output cannot be achieved immediately, a second sequence of input vectors must be applied in order to propagate the state difference to the output. Methods for combining the Boolean difference analysis with techniques for deriving the required input vector sequence are discussed.
Download or read book Fault Masking in Combinational Logic Circuits written by Stanford University Stanford Electronics Laboratories. Digital Systems Laboratory and published by . This book was released on 1974 with total page 40 pages. Available in PDF, EPUB and Kindle. Book excerpt:
