Download or read book Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm written by Uwe Gläser and published by . This book was released on 1994 with total page 22 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Parallel Computing Fundamentals Applications and New Directions written by E.H. D'Hollander and published by Elsevier. This book was released on 1998-07-22 with total page 765 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume gives an overview of the state-of-the-art with respect to the development of all types of parallel computers and their application to a wide range of problem areas. The international conference on parallel computing ParCo97 (Parallel Computing 97) was held in Bonn, Germany from 19 to 22 September 1997. The first conference in this biannual series was held in 1983 in Berlin. Further conferences were held in Leiden (The Netherlands), London (UK), Grenoble (France) and Gent (Belgium). From the outset the aim with the ParCo (Parallel Computing) conferences was to promote the application of parallel computers to solve real life problems. In the case of ParCo97 a new milestone was reached in that more than half of the papers and posters presented were concerned with application aspects. This fact reflects the coming of age of parallel computing. Some 200 papers were submitted to the Program Committee by authors from all over the world. The final programme consisted of four invited papers, 71 contributed scientific/industrial papers and 45 posters. In addition a panel discussion on Parallel Computing and the Evolution of Cyberspace was held. During and after the conference all final contributions were refereed. Only those papers and posters accepted during this final screening process are included in this volume. The practical emphasis of the conference was accentuated by an industrial exhibition where companies demonstrated the newest developments in parallel processing equipment and software. Speakers from participating companies presented papers in industrial sessions in which new developments in parallel computing were reported.
Download or read book The Computer Engineering Handbook written by Vojin G. Oklobdzija and published by CRC Press. This book was released on 2001-12-26 with total page 1409 pages. Available in PDF, EPUB and Kindle. Book excerpt: There is arguably no field in greater need of a comprehensive handbook than computer engineering. The unparalleled rate of technological advancement, the explosion of computer applications, and the now-in-progress migration to a wireless world have made it difficult for engineers to keep up with all the developments in specialties outside their own
Download or read book On line Error Detection and Fast Recover Techniques for Dependable Embedded Processors written by Matthias Pflanz and published by Springer Science & Business Media. This book was released on 2002-02-27 with total page 133 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents a new approach to on-line observation and concurrent checking of processors by refining and improving known techniques and introducing new ideas. The proposed on-line error detection and fast recover techniques support and complement other established methods. In combination with other on-line observation priniciples and with a combined hardware-software test, these techniques are used to fulfill a complete self-check scheme for an embedded processor.
Download or read book Formal Equivalence Checking and Design Debugging written by Shi-Yu Huang and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 238 pages. Available in PDF, EPUB and Kindle. Book excerpt: Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley
Download or read book A multi level hierarchical sequential circuit test generation algorithm written by Chun-Hung Chen and published by . This book was released on 1992 with total page 188 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Euro DAC 95 European Design Automation Conference with Euro VHDL written by and published by Institute of Electrical & Electronics Engineers(IEEE). This book was released on 1995 with total page 648 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Proceedings written by and published by . This book was released on 1995 with total page 648 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book EURO DAC written by and published by . This book was released on 1995 with total page 648 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Index to IEEE Publications written by Institute of Electrical and Electronics Engineers and published by . This book was released on 1996 with total page 1208 pages. Available in PDF, EPUB and Kindle. Book excerpt: Issues for 1973- cover the entire IEEE technical literature.
Download or read book Applied Science Technology Index written by and published by . This book was released on 1996 with total page 1720 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Delay Test Generation for Synchronous Sequential Circuits written by S. Devadas and published by . This book was released on 1989 with total page 11 pages. Available in PDF, EPUB and Kindle. Book excerpt: We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented. (RRH).
Download or read book Speeding Up a Procedure for Compact Test Generation for Synchronous Sequential Circuits written by Dayanand K. Reddy and published by . This book was released on 1996 with total page 78 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book An Approach to Test Pattern Generation for Synchronous Sequential Circuits written by Robert Stewart Lewis and published by . This book was released on 1967 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Automatic Test Pattern Generation for Synchronous Sequential Circuits written by Marinus Hendrik Konijnenburg and published by . This book was released on 1998 with total page 226 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test Generation and Partial Scan Design for Synchronous Sequential Circuits written by Dongho Lee and published by . This book was released on 1992 with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test Generation for Detecting Multiple Stuck Faults in Synchronous Sequential Circuits Using Boolean Difference and Transition Matrix Techniques written by Thiep V. Nguyen and published by . This book was released on 1993 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is a mathematical concept which has proved its usefulness in the study of single and multiple stuck-at faults in combinational circuits. This tool of analysis was extended to cover multiple stuck-at faults in synchronous sequential circuits as well. In this dissertation, modifications to previous work are presented, together with the development of a new method for deriving the required shortest test sequence to detect a specified multiple fault. First, the vector Boolean difference technique is utilized to determine the input vector that will produce a difference in output between the fault-free and faulty circuits with both starting in the same initial state. If that detection cannot be achieved immediately, then the state transition matrices of both circuits are combined and used to form a matrix of detecting state pairs. Each of these pairs comprises of the present states of both circuits for which an output difference will be detected by an input vector. The detecting tree is then built leading the two circuits from the same initial state to the first detecting state found to complete the search for the shortest test sequence. Besides being able to identify, at an early stage, faults that are undetectable, this algorithm guarantees the generation of a shortest test sequence, if one exists, for every multiple stuck-at fault in a synchronous sequential circuit having a synchronizing sequence or a known initial state. A computer program was also written as a tool to automatically generate test sequences for detecting single or multiple faults in both combinational and synchronous sequential circuits.
