Download or read book Fault Diagnosis in Combinational Logic Networks written by Robert B. Sieffert and published by . This book was released on 1975 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fault Diagnosis of Multiple Output Combinational Logic Networks written by Heramb Singh and published by . This book was released on 1971 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fault Detection Tests for Combinational Logic Networks written by Daniel Charles Scavezze and published by . This book was released on 1975 with total page 162 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Multiple Fault Diagnosis in Combinational Networks written by Charles Wei-Yuan Cha and published by . This book was released on 1974 with total page 114 pages. Available in PDF, EPUB and Kindle. Book excerpt: A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.

Download or read book A Study of Fault Diagnosis of Sequential Logic Networks written by B. D. Carroll and published by . This book was released on 1974 with total page 25 pages. Available in PDF, EPUB and Kindle. Book excerpt: The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.

Download or read book Sequential Decision Trees for Fault Diagnosis in Combinational Logic Networks written by Doctor Israel Koren and published by . This book was released on 1973 with total page 30 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book On Fault Diagnosis written by Louis Gwo-Jiun Chu and published by . This book was released on 1976 with total page 334 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fault Analysis of Combinational Logic Networks written by Lung-Hsiung Chang and published by . This book was released on 1974 with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fault Detection Methods in Combinational Digital Logic Networks written by Harold M. Levy and published by . This book was released on 1973 with total page 133 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ability to test a digital network as simply as possible has become quite important recently due to advances in integrated circuit technology and the consequent increases in the complexity of the networks being produced. The paper presents several existing methods of 'fault detection test generation'. A new approach to the problem of finding a minimal test set is then presented. The test set is obtained by solving a set of equations which are obtained directly from the network. It is shown that the solutions to these equations constitute a complete test set both for a nonreconvergent fanout network and for a reconvergent fanout network. A general solution procedure is presented which will generate a minimal test set for any network. An algorithm for generating a minimal test set for a nonreconvergent fanout network is also presented. (Author).

Download or read book Fault Detection in Combinational Networks written by Alexander Rahm and published by . This book was released on 1967 with total page 92 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This paper presents an algorithm for locating a failure in combinational logic networks, which is a problem of importance in the maintenance of computer systems. The procedure is based on the "path sensitizing" idea for fault detection. The networks considered are non-redundant, consisting of AND, OR, and NOT elements. The class of faults investigated is that which causes a connection to appear to be logically suck-at-one or stuck-at-zero, and only single failures are treated. It is shown that the failure is generally located to a specific "fault group"--Abstract, leaf 2.

Download or read book Fault Detection Methods in Combinational Ditital Logic Networks written by Harold M. Levy and published by . This book was released on 1972 with total page 246 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Detection of Single Faults in Combinational Logic Networks written by Dewayne Alan Spires and published by . This book was released on 1969 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Automated Multiple Fault Test Generation for Combinational Networks written by Robert A. Hendrix and published by . This book was released on 1976 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.

Download or read book Efficient Generation of Minimum Fault Test Schedules for Combinational Logic Networks written by William Alfred Hornfeck and published by . This book was released on 1971 with total page 190 pages. Available in PDF, EPUB and Kindle. Book excerpt: A number of fault detection procedures for combinational logic networks are discussed and efficient algorithms are developed for the automatic generation of network test inputs. Each of the algorithms is specialized in the sense that each is designed to generate tests for a specific class of logic networks. The analysis and development of the algorithms is based on the assumption of a single error in the form of a struck-at-one or struck-at-zero fault. Algorithms are also included which can be used for no-fan-out networks, sum-of-products and product-of-sum networks, and factored realizations. Test schedules generated by the computer-aided procedures provide both a complete and minimum set of test inputs for the different types of logic networks considered. (Author).

Download or read book Fault Equivalence in Combinational Logic Networks written by Stanford University Stanford Electronics Laboratories. Digital Systems Laboratory and published by . This book was released on 1971 with total page 42 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Study of Digital Network Structure and Its Relation to Fault Diagnosis written by John Patrick Hayes and published by . This book was released on 1970 with total page 272 pages. Available in PDF, EPUB and Kindle. Book excerpt: A network model, is introduced for the study of fault diagnosis in digital logic networks. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network can be obtained. The use of this model greatly simplifies fault analysis and test generation. The structure of the classes of indistinguishable faults in normal NAND networks is studied. It is shown that for certain types of networks, the indistinguishability classes can be characterized in a very simple manner. The conditions under which masking can occur are examined. These conditions lead to efficient methods for generating multiple-fault detection test sets. Some general bounds for the number of tests required by a network are examined. It is proven that for a n-input fanout-free network, the cardinality of any minimal detection or location test set lies between 2(square root of n) and 2n. It is argued that a 2-level realization of a random n-variable function requires, on the average, 2 to the (n-1) power tests to detect all faults. It is shown that for certain classes of functions there exists multi-level realizations which require relatively few tests, and for which complete detection test sets can easily be generated. (Author).

Download or read book NBS Technical Note written by and published by . This book was released on 1979-08 with total page 52 pages. Available in PDF, EPUB and Kindle. Book excerpt: