Download or read book Error Detection Circuits written by Michael Gössel and published by McGraw-Hill Companies. This book was released on 1993 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: The first comprehensive description of systematic methods for designing optional error detection circuits. Table of Contents: Overview and Introduction; Combinatorial Error Detection Circuitry; Sequential Error Detection Circuits; Design Algorithms for Error Detection Circuits; Appendix; References; Index. 100 illustrations.
Download or read book Error Detecting Codes Self checking Circuits and Applications written by John F. Wakerly and published by North Holland. This book was released on 1978 with total page 254 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Error Detecting Logic for Digital Computers written by Frederick F. Sellers and published by . This book was released on 1968 with total page 328 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Error Detection Decoding and Error Correction for Circuit Codes written by John Christopher Beebee and published by . This book was released on 1972 with total page 264 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Concurrent Error Detection written by Steven Scott Gorshe and published by . This book was released on 2002 with total page 246 pages. Available in PDF, EPUB and Kindle. Book excerpt: Concurrent error detection (CED) is the detection of errors or faults in a circuit or data path concurrent with normal operation of that circuit. The general approach for CED is to calculate a check symbol for the inputs to the circuit under operation, predict the check symbol that will result for the output of the circuit for those inputs, and compare the predicted check symbol to the one that is actually calculated for the output. If the predicted and actual check symbols are different, an error or fault has been detected. The alternative to this check symbol prediction is to use a second copy of the circuit under operation and compare the results of the two circuits. For some classes of circuits the prediction of the output check symbol can require less circuitry than a second copy of the circuit being tested. Four examples of these types of circuits are examined in this dissertation: Arithmetic Logic Units (ALUs), array multipliers, self-synchronous scrambler-descrambler pairs with their intervening data path, and switch fabrics. Faults in integrated circuits tend to produce unidirectional errors. Unidirectional errors are those in which all of the errors are in the same direction (e.g., 0 to 1 errors) within the block of data covered by a given check symbol. For this reason, codes that are optimized for unidirectional errors are the focus of investigation for most of the applications. In particular, the Bose-Lin codes are examined for those applications where unidirectional errors are expected to be typical. In order to examine the performance of the Bose-Lin codes in one of these applications, it was necessary to determine the theoretical performance for Bose- Lin codes for error rates beyond what had been previously studied. This analysis of Bose-Lin codes with large numbers of "burst" errors also included a further generalization of the codes.
Download or read book Error Detection and Location of Combinational Circuits written by Yun-chung Cho and published by . This book was released on 1970 with total page 52 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book New Methods of Concurrent Checking written by Michael Gössel and published by Springer Science & Business Media. This book was released on 2008-04-26 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: Computers are everywhere around us. We, for example, as air passengers, car drivers, laptop users with Internet connection, cell phone owners, hospital patients, inhabitants in the vicinity of a nuclear power station, students in a digital library or customers in a supermarket are dependent on their correct operation. Computers are incredibly fast, inexpensive and equipped with almost unimag- able large storage capacity. Up to 100 million transistors per chip are quite common today - a single transistor for each citizen of a large capital city in the world can be 2 easily accommodated on an ordinary chip. The size of such a chip is less than 1 cm . This is a fantastic achievement for an unbelievably low price. However, the very small and rapidly decreasing dimensions of the transistors and their connections over the years are also the reason for growing problems with reliability that will dramatically increase for the nano-technologies in the near future. Can we always trust computers? Are computers always reliable? Are chips suf- ciently tested with respect to all possible permanent faults if we buy them at a low price or have errors due to undetected permanent faults to be discovered by c- current checking? Besides permanent faults, many temporary or transient faults are also to be expected.
Download or read book A Concurrent Timing Error Detection Circuit for CMOS written by Christopher G. Knight and published by . This book was released on 1997 with total page 128 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CRL written by and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Computer Communication Systems Data Circuits Error Detection Data Links written by Henri Nussbaumer and published by Wiley. This book was released on 1990-02-02 with total page 282 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book An Ultra Fast All Optical Error Detection and Correction Circuit Based on Spectral Logic written by and published by . This book was released on 2000 with total page 11 pages. Available in PDF, EPUB and Kindle. Book excerpt: All-optical logic circuits based on the polarization properties of non-degenerate four-wave mixing are proposed. It is shown that higher-level Boolean operations involving several bits can be implemented without resorting to the standard 2-input gates. As a simple illustration of the idea, a circuit performing error correction on a (3, 1) Hamming Code is demonstrated. Error-free performance (Bit Error Rate of
Download or read book Codes for Error Detection written by Torleiv Kl?ve and published by World Scientific. This book was released on 2007 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt: There are two basic methods of error control for communication, both involving coding of the messages. With forward error correction, the codes are used to detect and correct errors. In a repeat request system, the codes are used to detect errors and, if there are errors, request a retransmission. Error detection is usually much simpler to implement than error correction and is widely used. However, it is given a very cursory treatment in almost all textbooks on coding theory. Only a few older books are devoted to error detecting codes. This book begins with a short introduction to the theory of block codes with emphasis on the parts important for error detection. The weight distribution is particularly important for this application and is treated in more detail than in most books on error correction. A detailed account of the known results on the probability of undetected error on the q-ary symmetric channel is also given.
Download or read book Concurrent Error Detection with Latency in Sequential Circuits written by Lawrence Paul Holmquist and published by . This book was released on 1989 with total page 386 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Error Detecting Codes Self checking Circuits and Applications written by John F. Wakerly and published by North Holland. This book was released on 1978 with total page 256 pages. Available in PDF, EPUB and Kindle. Book excerpt: Error-detecting codes; Self-checking circuits; Data paths and memory; Arithmetic operations; Logical operations; Microprogrammed control units; Example design of a self-checking processor.
Download or read book A Comprehensive Fault Model for Concurrent Error Detection in MOS Circuits written by Daniel Lee Halperin and published by . This book was released on 1984 with total page 412 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book On line Error Detection and Fast Recover Techniques for Dependable Embedded Processors written by Matthias Pflanz and published by Springer. This book was released on 2003-07-31 with total page 133 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents a new approach to on-line observation and concurrent checking of processors by refining and improving known techniques and introducing new ideas.The proposed on-line error detection and fast recover techniques support and complement other established methods. In combination with other on-line observation priniciples and with a combined hardware-software test, these techniques are used to fulfill a complete self-check scheme for an embedded processor.
Download or read book Logic Synthesis for Concurrent Error Detection written by Stanford University. Computer Systems Laboratory and published by . This book was released on 1993 with total page 30 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "The structure of a circuit determines how the effects of a fault can propagate and hence affects the cost of concurrent error detection. By considering circuit structure during logic optimization, the overall cost of a concurrently checked circuit can be minimized. This report presents a new technique called structure-constrained logic optimization (SCLO) that optimizes a circuit under the constraint that faults in the resulting circuit can produce only a prescribed set of errors. Using SCLO, circuits can be optimized for various concurrent error detection schemes allowing the overall cost for each scheme to be compared. A technique for quickly estimating the size of a circuit under different structural constraints is described. This technique enables rapid exploration of the design space for concurrently checked circuits. A new method for the automated synthesis of self-checking circuit implementations for arbitrary combinational circuits is also presented. It consists of an algorithm that determines the best parity-check code for encoding the output of a given circuit, and then uses SCLO to produce the functional circuit which is augmented with a checker to form a self-checking circuit. This synthesis method provides fully automated design, explores a larger design space than other methods, and uses simple checkers. It has been implemented by making modifications to SIS (an updated version of MIS [Brayton 87a]), and results for several MCNC combinational benchmark circuits are given. In most cases, a substantial reduction in overhead compared to a duplicate-and-compare implementation is achieved."
