Download or read book Error Detection and Location of Combinational Circuits written by Yun-chung Cho and published by . This book was released on 1970 with total page 52 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Automatic Design Error Correction of Combinational Circuits written by Dirk W. Hoffmann and published by . This book was released on 2001 with total page 178 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Error Detection Circuits written by Michael Gössel and published by McGraw-Hill Companies. This book was released on 1993 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: The first comprehensive description of systematic methods for designing optional error detection circuits. Table of Contents: Overview and Introduction; Combinatorial Error Detection Circuitry; Sequential Error Detection Circuits; Design Algorithms for Error Detection Circuits; Appendix; References; Index. 100 illustrations.
Download or read book Self Checking and Fault Tolerant Digital Design written by Parag K. Lala and published by Morgan Kaufmann. This book was released on 2001 with total page 238 pages. Available in PDF, EPUB and Kindle. Book excerpt: With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation. Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems. Features: Introduces reliability theory and the importance of maintainability Presents coding and the construction of several error detecting and correcting codes Discusses in depth, the available techniques for fail-safe design of combinational circuits Details checker design techniques for detecting erroneous bits and encoding output of self-checking circuits Demonstrates how to design self-checking sequential circuits, including a technique for fail-safe state machine design
Download or read book Error Detecting Logic for Digital Computers written by Frederick F. Sellers and published by . This book was released on 1968 with total page 328 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Logic Synthesis for Concurrent Error Detection written by Stanford University. Computer Systems Laboratory and published by . This book was released on 1993 with total page 30 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "The structure of a circuit determines how the effects of a fault can propagate and hence affects the cost of concurrent error detection. By considering circuit structure during logic optimization, the overall cost of a concurrently checked circuit can be minimized. This report presents a new technique called structure-constrained logic optimization (SCLO) that optimizes a circuit under the constraint that faults in the resulting circuit can produce only a prescribed set of errors. Using SCLO, circuits can be optimized for various concurrent error detection schemes allowing the overall cost for each scheme to be compared. A technique for quickly estimating the size of a circuit under different structural constraints is described. This technique enables rapid exploration of the design space for concurrently checked circuits. A new method for the automated synthesis of self-checking circuit implementations for arbitrary combinational circuits is also presented. It consists of an algorithm that determines the best parity-check code for encoding the output of a given circuit, and then uses SCLO to produce the functional circuit which is augmented with a checker to form a self-checking circuit. This synthesis method provides fully automated design, explores a larger design space than other methods, and uses simple checkers. It has been implemented by making modifications to SIS (an updated version of MIS [Brayton 87a]), and results for several MCNC combinational benchmark circuits are given. In most cases, a substantial reduction in overhead compared to a duplicate-and-compare implementation is achieved."
Download or read book Error Detecting Codes Self checking Circuits and Applications written by John F. Wakerly and published by North Holland. This book was released on 1978 with total page 254 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Spectral Techniques and Fault Detection written by Marg Karpovsky and published by Elsevier. This book was released on 2012-12-02 with total page 619 pages. Available in PDF, EPUB and Kindle. Book excerpt: Spectral Techniques and Fault Detection focuses on the spectral techniques for the analysis, testing, and design of digital devices. This book discusses the error detection and correction in digital devices. Organized into 10 chapters, this book starts with an overview of the concepts and tools to evaluate the applicability of various spectral approaches and fault-detection techniques to the design. This text then describes the class of generalized Programmable Logic Array configurations called Encoded PLAs. Other chapters consider the two-sided Chrestenson Transform to the analysis of some pattern properties. This book describes as well a certain type of cellular arrays for highly parallel processing, namely, three-dimensional arrays. The final chapter deals with the system design methods that allow and encourage designers to incorporate the necessary distributed error correction throughout any digital system. This book is a valuable resource for graduate students and engineers working in the fields of logic design, spectral techniques, testing, and self-testing of digital devices.
Download or read book Functional Method for Multiple Fault Detection and Location in Combinational Circuits written by Ka Ngow Wong and published by . This book was released on 1974 with total page 124 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Equivalence Checking of Digital Circuits written by Paul Molitor and published by Springer Science & Business Media. This book was released on 2007-05-08 with total page 263 pages. Available in PDF, EPUB and Kindle. Book excerpt: Hardware veri?cation is the process of checking whether a design conforms to its speci?cations of functionality and timing. In today’s design processes it becomes more and more important. Very large scale integrated (VLSI) circuits and the resulting digital systems have conquered a place in almost all areas of our life, even in security sensitive applications. Complex digital systems control airplanes, have been used in banks and on intensive-care units. Hence, the demand for error-free designs is more important than ever. In addition, economic reasons underline this demand as well. The design and production process of present day VLSI-circuits is highly time- and cost-intensive. Mo- over, it is nearly impossible to repair integrated circuits. Thus, it is desirable to detect design errors early in the design process and not just after producing the prototype chip. All these facts are re?ected by developing and prod- tion statistics of present day companies. For example, In?neon Technologies [118] assumed that about 60% to 80% of the overall design time was spent for veri?cation in 2000. Other sources cite the 3-to-1 head count ratio between veri?cation engineers and logic designers. This shows that verifying logical correctness of the design of hardware systems is a major gate to the problem of time-to-market (cf. [113]). With the chip complexity constantly increasing, the dif?culty as well as the - portance of functional veri?cation of new product designs has been increased. It is not only more important to get error-free designs.
Download or read book Testing for single intermittent failures in combinational circuits by maximizing the probability of fault detection written by Stanford University Stanford Electronics Laboratories. Digital Systems Laboratory and published by . This book was released on 1977 with total page 54 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Code Design for Dependable Systems written by Eiji Fujiwara and published by John Wiley & Sons. This book was released on 2006-05-26 with total page 718 pages. Available in PDF, EPUB and Kindle. Book excerpt: Theoretical and practical tools to master matrix code design strategy and technique Error correcting and detecting codes are essential to improving system reliability and have popularly been applied to computer systems and communication systems. Coding theory has been studied mainly using the code generator polynomials; hence, the codes are sometimes called polynomial codes. On the other hand, the codes designed by parity check matrices are referred to in this book as matrix codes. This timely book focuses on the design theory for matrix codes and their practical applications for the improvement of system reliability. As the author effectively demonstrates, matrix codes are far more flexible than polynomial codes, as they are capable of expressing various types of code functions. In contrast to other coding theory publications, this one does not burden its readers with unnecessary polynomial algebra, but rather focuses on the essentials needed to understand and take full advantage of matrix code constructions and designs. Readers are presented with a full array of theoretical and practical tools to master the fine points of matrix code design strategy and technique: * Code designs are presented in relation to practical applications, such as high-speed semiconductor memories, mass memories of disks and tapes, logic circuits and systems, data entry systems, and distributed storage systems * New classes of matrix codes, such as error locating codes, spotty byte error control codes, and unequal error control codes, are introduced along with their applications * A new parallel decoding algorithm of the burst error control codes is demonstrated In addition to the treatment of matrix codes, the author provides readers with a general overview of the latest developments and advances in the field of code design. Examples, figures, and exercises are fully provided in each chapter to illustrate concepts and engage the reader in designing actual code and solving real problems. The matrix codes presented with practical parameter settings will be very useful for practicing engineers and researchers. References lead to additional material so readers can explore advanced topics in depth. Engineers, researchers, and designers involved in dependable system design and code design research will find the unique focus and perspective of this practical guide and reference helpful in finding solutions to many key industry problems. It also can serve as a coursebook for graduate and advanced undergraduate students.
Download or read book New Methods of Concurrent Checking written by Michael Gössel and published by Springer Science & Business Media. This book was released on 2008-04-26 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: Computers are everywhere around us. We, for example, as air passengers, car drivers, laptop users with Internet connection, cell phone owners, hospital patients, inhabitants in the vicinity of a nuclear power station, students in a digital library or customers in a supermarket are dependent on their correct operation. Computers are incredibly fast, inexpensive and equipped with almost unimag- able large storage capacity. Up to 100 million transistors per chip are quite common today - a single transistor for each citizen of a large capital city in the world can be 2 easily accommodated on an ordinary chip. The size of such a chip is less than 1 cm . This is a fantastic achievement for an unbelievably low price. However, the very small and rapidly decreasing dimensions of the transistors and their connections over the years are also the reason for growing problems with reliability that will dramatically increase for the nano-technologies in the near future. Can we always trust computers? Are computers always reliable? Are chips suf- ciently tested with respect to all possible permanent faults if we buy them at a low price or have errors due to undetected permanent faults to be discovered by c- current checking? Besides permanent faults, many temporary or transient faults are also to be expected.
Download or read book New Methods for Fault Detection and Location in Large Combination Circuits written by Natvar G. Patel and published by . This book was released on 1974 with total page 212 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Efficient Design of Variation Resilient Ultra Low Energy Digital Processors written by Hans Reyserhove and published by Springer. This book was released on 2019-03-27 with total page 227 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book enables readers to achieve ultra-low energy digital system performance. The author’s main focus is the energy consumption of microcontroller architectures in digital (sub)-systems. The book covers a broad range of topics extensively: from circuits through design strategy to system architectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy.
Download or read book Self Checking of Multi Output Combinational Circuits Using Forced Parity Technique written by Danny Chih-Chun Ko and published by . This book was released on 1973 with total page 159 pages. Available in PDF, EPUB and Kindle. Book excerpt: One integral part of a self-checking system is an appropriate error detecting circuit. The error signal provided can be used to stop computation, signal for manual repair, or initiate automatic reconfiguration. In the report error detecting schemes for combinational circuits are investigated from the hardware redundancy viewpoint. It is well-known that any circuit can be checked by the technique of complete duplication. The redundancy ratio obtained is higher than 2:1. The technique presented in this dissertation is called Forced-Parity Checking. Its concept is derived from conventional parity checking technique which is applicable only for odd numbers of errors, yet it can detect errors of any degree. Since some circuits lend themselves to be checked more efficiently by one technique than by another, this technique is by no means expected to achieve a low redundancy ratio for every circuit. The main objective is to generalize and formalize a design procedure which, when applied to a circuit, may yield a redundancy ratio below the known lower bound. (Modified author abstract).
Download or read book On Line Testing for VLSI written by Michael Nicolaidis and published by Springer Science & Business Media. This book was released on 1998-04-30 with total page 166 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.
