Download or read book Energy Efficient Circuit Design Using Nanoelectromechanical Relays written by Ramakrishnan Venkatasubramanian and published by . This book was released on 2012 with total page 280 pages. Available in PDF, EPUB and Kindle. Book excerpt: In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects.

Download or read book Advanced Relay Design and Technology for Energy Efficient Electronics written by Jaeseok Jeon and published by . This book was released on 2011 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the era of traditional Complementary-Metal-Oxide-Semiconductor (CMOS) technology scaling is coming to an end, continual improvements in integrated-circuit (IC) performance and cost per function are becoming difficult to achieve without increasing power density. This necessitates the investigation of alternate device technologies that surmount the fundamental CMOS energy-efficiency limit and hence enable ultra-low-power ICs. To that end, a nano-electro-mechanical (NEM) relay technology is promising, because of its immeasurably low off-state leakage current and abrupt turn-on behavior, which provide for zero static power consumption and potentially very low dynamic power consumption. In this dissertation, relay design and process technology improvements, which led to the successful demonstration of relay-based digital IC building blocks, are discussed from both device- and circuit-level perspectives. A non-volatile (NV) memory relay design that can enable embedding of NV memory with relay-based logic circuits is also discussed. In addition, multielectrode relays that can lead to smarter design and compact implementation of zero-leakage digital integrated circuits are discussed.

Download or read book VLSI written by Tomasz Wojcicki and published by CRC Press. This book was released on 2017-12-19 with total page 490 pages. Available in PDF, EPUB and Kindle. Book excerpt: Recently the world celebrated the 60th anniversary of the invention of the first transistor. The first integrated circuit (IC) was built a decade later, with the first microprocessor designed in the early 1970s. Today, ICs are a part of nearly every aspect of our daily lives. They help us live longer and more comfortably, and do more, faster. All this is possible because of the relentless search for new materials, circuit designs, and ideas happening on a daily basis at industrial and academic institutions around the globe. Showcasing the latest advances in very-large-scale integrated (VLSI) circuits, VLSI: Circuits for Emerging Applications provides a balanced view of industrial and academic developments beyond silicon and complementary metal–oxide–semiconductor (CMOS) technology. From quantum-dot cellular automata (QCA) to chips for cochlear implants, this must-have resource: Investigates the trend of combining multiple cores in a single chip to boost performance of the overall system Describes a novel approach to enable physically unclonable functions (PUFs) using intrinsic features of a VLSI chip Examines the VLSI implementations of major symmetric and asymmetric key cryptographic algorithms, hash functions, and digital signatures Discusses nonvolatile memories such as resistive random-access memory (Re-RAM), magneto-resistive RAM (MRAM), and floating-body RAM (FB-RAM) Explores organic transistors, soft errors, photonics, nanoelectromechanical (NEM) relays, reversible computation, bioinformatics, asynchronous logic, and more VLSI: Circuits for Emerging Applications presents cutting-edge research, design architectures, materials, and uses for VLSI circuits, offering valuable insight into the current state of the art of micro- and nanoelectronics.

Download or read book Micro Relay Technology for Energy Efficient Integrated Circuits written by Hei Kam and published by Springer. This book was released on 2014-10-16 with total page 190 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers, and highlights the importance of co-design across design hierarchies when trying to optimize system performance (in this case, energy-efficiency). The book will also appeal to researchers and engineers focused on semiconductor, integrated circuits, and energy efficient electronics.

Download or read book Floating point Unit FPU Designs with Nano electromechanical NEM Relays written by Sumit Dutta (S.M.) and published by . This book was released on 2013 with total page 74 pages. Available in PDF, EPUB and Kindle. Book excerpt: Nano-electromechanical (NEM) relays are an alternative to CMOS transistors as the fabric of digital circuits. Circuits with NEM relays offer energy-efficiency benefits over CMOS since they have zero leakage power and are strategically designed to maintain throughput that is competitive with CMOS despite their slow actuation times. The floating-point unit (FPU) is the most complex arithmetic unit in a computational system. This thesis investigates if the energy-efficiency promise of NEM relays demonstrated before on smaller circuit blocks holds for complex computational structures such as the FPU. The energy, performance, and area trade-offs of FPU designs with NEM relays are examined and compared with that of state-of-the-art CMOS designs in an equivalent scaled process. Circuits that are critical path bottlenecks, including primarily the leading zero detector (LZD) and leading zero anticipator (LZA) blocks, are carefully identified and optimized for low latency and device count. We manage to drop the NEM relay FPU latency from 71 mechanical delays in a CMOS-style implementation to 16 mechanical delays in a NEM relay pass-logic style implementation. The FPU designed with NEM relays features 15x lower energy per operation compared to CMOS.

Download or read book ICT Energy Concepts for Energy Efficiency and Sustainability written by Giorgos Fagas and published by BoD – Books on Demand. This book was released on 2017-03-22 with total page 252 pages. Available in PDF, EPUB and Kindle. Book excerpt: In a previous volume (ICT-Energy-Concepts Towards Zero-Power ICT; referenced below as Vol. 1), we addressed some of the fundamentals related to bridging the gap between the amount of energy required to operate portable/mobile ICT systems and the amount of energy available from ambient sources. The only viable solution appears to be to attack the gap from both sides, i.e. to reduce the amount of energy dissipated during computation and to improve the efficiency in energy-harvesting technologies. In this book, we build on those concepts and continue the discussion on energy efficiency and sustainability by addressing the minimisation of energy consumption at different levels across the ICT system stack, from hardware to software, as well as discussing energy consumption issues in high-performance computing (HPC), data centres and communication in sensor networks. This book was realised thanks to the contribution of the project ‘Coordinating Research Efforts of the ICT-Energy Community’ funded from the European Union under the Future and Emerging Technologies (FET) area of the Seventh Framework Programme for Research and Technological Development (grant agreement n. 611004).

Download or read book Design and Demonstration of Integrated Micro electro mechanical Relay Circuits for VLSI Applications written by Hossein Fariborzi and published by . This book was released on 2013 with total page 121 pages. Available in PDF, EPUB and Kindle. Book excerpt: Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade and for technology nodes below 90 nm, the scaling of threshold and supply voltages has slowed, as a result of subthreshold leakage, and power density has increased with each new technology node. This has forced a move toward multi-core architectures, but the energy efficiency benefits of parallelism are limited by the sub-thresahold leakage and the minimum energy point for a given function. Avoiding this roadblock requires an alternative device with more ideal switching characteristics. One promising class of such devices is the electro-statically actuated micro-electro-mechanical (MEM) relay which offers zero leakage current and abrupt turn-on behavior. Although a MEM relay is inherently slower than a CMOS transistor due to the mechanical movement, we have developed circuit design methodologies to mitigate this problem at the system level. This thesis explores such design optimization techniques and investigates the viability of MEM relays as an alternative switching technology for very-large scale integration (VLSI) applications. In the first part of this thesis, the feasibility of MEM relays for power management applications is discussed. Due to their negligibly low leakage, in certain applications, chips utilizing power gates built with MEM relays can achieve lower total energy than those built with CMOS transistors. A simple comparative analysis is presented and provides design guidelines and energy savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. We also demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based pulse generator suitable for self-timed operation. Going beyond power-gating applications, this work also describes circuit techniques and trade-offs for logic design with MEM-relays, focusing on multipliers which are commonly known as the most complex arithmetic units in a digital system. These techniques leverage the large disparity between mechanical and electrical time-constants of a relay, partitioning the logic into large, complex gates to minimize the effect of mechanical delay and improve circuit performance. At the component design level, innovations in compressor unit design minimize the required number of relays for each block and facilitate component cascading with no delay penalty. We analyze the area/energy/delay trade-offs vs. CMOS designs, for typical bit-widths, and show that scaled relays offer 10-20x lower energy per operation for moderate throughputs (

Download or read book Microelectronics to Nanoelectronics written by Anupama B. Kaul and published by CRC Press. This book was released on 2017-12-19 with total page 464 pages. Available in PDF, EPUB and Kindle. Book excerpt: Composed of contributions from top experts, Microelectronics to Nanoelectronics: Materials, Devices and Manufacturability offers a detailed overview of important recent scientific and technological developments in the rapidly evolving nanoelectronics arena. Under the editorial guidance and technical expertise of noted materials scientist Anupama B. Kaul of California Institute of Technology’s Jet Propulsion Lab, this book captures the ascent of microelectronics into the nanoscale realm. It addresses a wide variety of important scientific and technological issues in nanoelectronics research and development. The book also showcases some key application areas of micro-electro-mechanical-systems (MEMS) that have reached the commercial realm. Capitalizing on Dr. Kaul’s considerable technical experience with micro- and nanotechnologies and her extensive research in prestigious academic and industrial labs, the book offers a fresh perspective on application-driven research in micro- and nanoelectronics, including MEMS. Chapters explore how rapid developments in this area are transitioning from the lab to the market, where new and exciting materials, devices, and manufacturing technologies are revolutionizing the electronics industry. Although many micro- and nanotechnologies still face major scientific and technological challenges and remain within the realm of academic research labs, rapid advances in this area have led to the recent emergence of new applications and markets. This handbook encapsulates that exciting recent progress by providing high-quality content contributed by international experts from academia, leading industrial institutions—such as Hewlett-Packard—and government laboratories including the U.S. Department of Energy’s Sandia National Laboratory. Offering something for everyone, from students to scientists to entrepreneurs, this book showcases the broad spectrum of cutting-edge technologies that show significant promise for electronics and related applications in which nanotechnology plays a key role.

Download or read book Nanoelectromechanical Relays for Low Power Applications written by Roozbeh Parsa and published by Stanford University. This book was released on 2011 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt: CMOS scaling has been very successful in generating small, fast, low cost electronics. However, in advanced CMOS nodes, the total power consumption is dominated by the static power dissipation, which is caused greatly by gate leakage, short channel effects, and finite subthreshold slope. Further scaling of CMOS only exacerbates these problems. Nanoelectromechanical (NEM) relays are promising devices for assisting CMOS systems by reducing the static power dissipation due to their zero leakage current, infinite subthreshold slope, and scalable actuation voltage. Electrostatically-actuated NEM relays are devices where the operation is based on the deformation of a flexible beam under the influence of electrostatic force in order to create a conducting path between two electrodes. This work studies the fabrication process development of sidewall-coated laterally-actuated NEM relays. The developed process enables decoupling of the mechanical and electrical properties of the relay, allowing independent optimization of each property and paving the path for creating a back-end-of-line (BEOL) compatible process. Furthermore, a major failure mechanism of NEM relays is beam-to-gate shorting after actuation. To ameliorate this problem, new designs with improved mechanical properties were simulated and tested. These designs utilize a stiff electrode and a compliant beam to eliminate undesired beam deformation near the gate electrode. These results in addition to variation studies, stress outcomes, and basic logic functionality of the NEM relays are shown.

Download or read book Nanoelectromechanical Relays for Low Power Digital Systems written by William Scott Lee and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Since the invention of the integrated circuit in the late 1950s, complementary-metal-oxide-semiconductor (CMOS) scaling has made microelectronics ubiquitous in our daily lives. As CMOS circuits scale, the leakage current increases exponentially. The subthreshold slope of a MOSFET is theoretically limited to 60 mV/decade. Nanoelectromechanical (NEM) relays offer an alternative switching mechanism that enables nearly zero off state leakage current and sharp switching characteristics. The NEM relays, however, have much longer switching times compared to CMOS transistors. Due to the increasing complexity of scaling, producing application specific integrated circuits (ASICs) has become cost prohibitive for all but the highest volume applications. To provide a cost effective means of accessing advanced technology nodes, flexible digital circuits also known as field programmable gate arrays (FPGAs) are becoming more popular for a wide variety of applications. A digital function implemented on an FPGA, however, requires up to 35X more area and 14X more power while operating at a lower speed compared to the same function built on an ASIC. By incorporating NEM relays and CMOS transistors together, the low leakage characteristics of the NEM relay can be combined with the fast switching speeds of CMOS transistors. In the first part of this work, we review recent efforts to fabricate NEM relays and efforts to utilize NEM relays to improve the performance of FPGAs. We investigate the use of NEM relays as configurable, routing switches that can replace both the CMOS pass transistors and the accompanying SRAM cell. By following this method and by selectively resizing and removing routing buffers, the hybrid CMOS-NEM relay FPGA can achieve a 2X, 2X, and 10X improvement in area, dynamic power, and leakage power, respectively, compared to a CMOS-only FPGA. Realizing these benefits requires NEM relays with sub-10 kOhm on resistance that can be fabricated with back-end-of-line (BEOL) compatible processes. The NEM relays must also have a sufficiently large hysteresis window and actuation voltages with tight distributions to satisfy the half-select programming requirements. In the second part of this work, we design and fabricate NEM relays to meet these metrics. Novel lateral relays with decoupled electrode regions and compliant contacts are demonstrated. Arrays of these relays are demonstrated with over 90% of the devices meeting the resistance requirement and over 90% of the devices meeting the programming requirements. Most of these devices are fabricated with polysilicon and titanium nitride as the structural layer and contact material, respectively. SiGe is investigated as an alternative, BEOL compatible structural layer. Hafnium diboride and ruthenium are explored as alternative contact materials; on-resistances as low as 1.4 kOhm and 1.2 kOhm, respectively, are demonstrated. Outside of hybrid applications that combine CMOS and NEM relays on the same circuit, NEM relay circuits have been proposed as a means of performing very low energy digital logic. In the third part of this work, we develop the six-terminal relay, explore its use as a digital logic element, and demonstrate a NEM relay inverter.

Download or read book Emerging Devices for Low Power and High Performance Nanosystems written by Simon Deleonibus and published by CRC Press. This book was released on 2018-12-13 with total page 410 pages. Available in PDF, EPUB and Kindle. Book excerpt: The history of information and communications technologies (ICT) has been paved by both evolutive paths and challenging alternatives, so-called emerging devices and architectures. Their introduction poses the issues of state variable definition, information processing, and process integration in 2D, above IC, and in 3D. This book reviews the capabilities of integrated nanosystems to match low power and high performance either by hybrid and heterogeneous CMOS in 2D/3D or by emerging devices for alternative sensing, actuating, data storage, and processing. The choice of future ICTs will need to take into account not only their energy efficiency but also their sustainability in the global ecosystem.

Download or read book Conception Et Fabrication Hybride 3D Monolithique de Relais NEMS Co integr s CMOS written by Giulia Usai and published by . This book was released on 2019 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This manuscript focuses on Nano-Electro-Mechanical (NEM) relays with electrostatic actuation for advanced logic and memory applications. The use of Nano-Electro-Mechanical relays was recently proposed for digital logic circuits in order to overcome the fundamental energy-efficiency limitations that mainstream CMOS technology is currently facing. The cumulated benefits of essentially Zero Off-State current and ultimately abrupt DC switching characteristics enable alleviating the power-performance trade-off as the supply voltage VDD is reduced. Additionally, for some particular switch designs (e.g. free of dielectric layers), an increased resistance to ionizing radiations is also anticipated, making such components valuable for defense or aerospace applications.However, NEM relays have intrinsic limitations in terms of integration density, endurance and operation frequency. Therefore, rather than considering them as technology that could replace MOSFETs, we adopt an intermediate approach that consists in using NEM relays as a complement to CMOS circuits (e.g.: buffers, non-volatile elements for SRAM and CAM), which can be fabricated in a 3D co-integration scheme. This approach mitigates the area penalty issue.The thesis explores the strength and the weakness of NEMS relays and identifies applications for which hybrid NEMS/CMOS circuits are potentially interesting.This work includes the manufacturing of prototype devices designed to be proof of concept for the identified applications. At first, NV NEM relays design and dimensioning through modelling and simulations was performed. Then NV NEM/CMOS circuits were validated trough simulations. This was followed by the tapeout and the process integration of monolithically co-integrated NEMS above CMOS. After wafer processing the devices were electrically characterized.This all-inclusive works allows identifying some crucial challenges that NEMS relays still have to face.

Download or read book Novel Material Integration for Reliable and Energy Efficient NEM Relay Technology written by I-Ru Chen and published by . This book was released on 2014 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: Energy-efficient switching devices have become ever more important with the emergence of ubiquitous computing. NEM relays are promising to complement CMOS transistors as circuit building blocks for future ultra-low-power information processing, and as such have recently attracted significant attention from the semiconductor industry and researchers. Relay technology potentially can overcome the energy efficiency limit for conventional CMOS technology due to several key characteristics, including zero OFF-state leakage, abrupt switching behavior, and potentially very low active energy consumption. However, two key issues must be addressed for relay technology to reach its full potential: surface oxide formation at the contacting surfaces leading to increased ON-state resistance after switching, and high switching voltages due to strain gradient present within the relay structure. This dissertation advances NEM relay technology by investigating solutions to both of these pressing issues. Ruthenium, whose native oxide is conductive, is proposed as the contacting material to improve relay ON-state resistance stability. Ruthenium-contact relays are fabricated after overcoming several process integration challenges, and show superior ON-state resistance stability in electrical measurements and extended device lifetime. The relay structural film is optimized via stress matching among all layers within the structure, to provide lower strain gradient (below 10E-3/μm) and hence lower switching voltage. These advancements in relay technology, along with the integration of a metallic interconnect layer, enable complex relay-based circuit demonstration. In addition to the experimental efforts, this dissertation theoretically analyzes the energy efficiency limit of a NEM switch, which is generally believed to be limited by the surface adhesion energy. New compact (

Download or read book Nano Electro Mechanical NEM Relay Devices and Technology for Ultra Low Energy Digital Integrated Circuits written by Rhesa Nathanael and published by . This book was released on 2012 with total page 268 pages. Available in PDF, EPUB and Kindle. Book excerpt: Complementary-Metal-Oxide-Semiconductor (CMOS) technology scaling has brought about an integrated circuits (IC) revolution over the past 40+ years, due to dramatic increases in IC functionality and performance, concomitant with reductions in cost per function. In the last decade, increasing power density has emerged to be the primary barrier to continued rapid advancement in IC technology, fundamentally due to non-zero transistor off-state leakage. While innovations in materials, transistor structures, and circuit/system architecture have enabled the semiconductor industry to continue to push the boundaries, a fundamental lower limit in energy per operation will eventually be reached. A more ideal switching device with zero off-state leakage becomes necessary. This dissertation proposes a solution to the CMOS power crisis via mechanical computing. Specifically, robust electro-mechanical relay technologies are developed for digital circuit application. A 4-Terminal (4T) relay design is firstly developed. Key technology features include tungsten contacts for high endurance; low-thermal-budget p+-poly-Si0.4Ge0.6 structure for post-CMOS process compatibility; Al2O3 as a reliable insulation material; dry release step to mitigate stiction; and folded-flexure design to mitigate the impact of residual stress. Fabricated relays show good conductance (RON IOFF ~ 10-14 A). Switching delay in the 100 ns range and endurance exceeding 109 on/off cycles is achieved with excellent device yield (> 95%). With relay design and process optimizations, pull-in voltage below 10 V with less than 1 V hysteresis is achieved. Miniaturization reduces the device footprint to 35[mu]m×50[mu]m, ~10% of the first generation device footprint (120[mu]m×150[mu]m). Relays with multiple source/drain electrodes and multiple gate electrodes are proposed for increased circuit functionality and reduced device count. Finally, simple relay-based logic circuits are demonstrated to show pathways to relay-based digital integrated circuits. The complementary inverter is the basis for all digital logic circuits and is investigated in depth. Relay-based logic gates are demonstrated using CMOS-like and relay-specific design approaches. Multi-input/multi-output relays are proposed to enable any complex logic function to be implemented compactly with only two relays.

Download or read book Nano Devices and Circuit Techniques for Low Energy Applications and Energy Harvesting written by Chong-Min Kyung and published by Springer. This book was released on 2015-07-16 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes the development of core technologies to address two of the most challenging issues in research for future IT platform development, namely innovative device design and reduction of energy consumption. Three key devices, the FinFET, the TunnelFET, and the electromechanical nanoswitch are described with extensive details of use for practical applications. Energy issues are also covered in a tutorial fashion from material physics, through device technology, to innovative circuit design. The strength of this book lies in its holistic approach dealing with material trends, state-of-the-art of key devices, new examples of circuits and systems applications. This is the first of three books based on the Integrated Smart Sensors research project, which describe the development of innovative devices, circuits, and system-level enabling technologies. The aim of the project was to develop common platforms on which various devices and sensors can be loaded, and to create systems offering significant improvements in information processing speed, energy usage, and size. The book contains extensive reference lists and with over 200 figures introduces the reader to the general subject in a tutorial style, also addressing the state-of-the-art, allowing it to be used as a guide for starting researchers in these fields.

Download or read book Design Considerations for Nano Electromechanical Relay Circuits written by Matthew Edmund Spencer and published by . This book was released on 2015 with total page 102 pages. Available in PDF, EPUB and Kindle. Book excerpt: Complementary metal oxide semiconductor (CMOS) technology has a minimum energy per operation, and that limitation is one of the myriad hurdles CMOS faces as it reaches small scales. This minimum energy is set by the balance between leakage energy and dynamic energy in subthreshold CMOS circuits, and sets floors on the achievable energy of digital units. A new, post-CMOS device with a sharper subthreshold slope than CMOS would be able to sidestep this minimum energy constraint. A candidate device called a nano-electromechancial (NEM) relay has recently emerged. NEM relays are small, integrated, capacitively-actuated, mechanical switches. The devices have demonstrated extremely high subthreshold slopes: ten orders of magnitude over a millivolt of swing. However, in the same lithographic process they are twenty times larger than a minimum sized CMOS device, their gate capacitance is ten times that of a minimum sized CMOS device, and their mechanical motion is an order of magnitude slower than a CMOS inverter. Can NEM relays improve digital systems even with these drawbacks? With proper circuit design, simulations say "yes". This dissertation examines three of the critical components of digital systems -- logic, timing, and memory -- and proposes NEM circuits which mitigate the weaknesses of the technology while achieving design goals. Simulations show that optimized relay logic, which arranges for all of the slow movement of relays to happen at the same time, can achieve an improvement of 10x in energy-per-operation below the CMOS minimum energy point at a penalty of 10x in delay and 3x in area. This logic style is experimentally demonstrated. In addition, relay latch based timing with staticization in the feedback path is simulated, which results in a working relay pipeline with zero mechanical delays of timing overhead. Finally, a new device called NEMory is proposed to build dense, non-volatile, mechanical memory. A hybrid NEMory/CMOS array is simulated, and its performance is compared to other memory solutions. The NEMory density is higher than any non-volatile memory except for multi-level cell, o-chip Flash, and its read and write energy are lower than any other non-volatile technology. Finally, the scaling and process limits of realizing mechanical devices are discussed in the context of future work.

Download or read book BDD based Logic Synthesis of MEM Relay Circuits written by Mingzhe Jiang and published by . This book was released on 2013 with total page 65 pages. Available in PDF, EPUB and Kindle. Book excerpt: As CMOS scaling begins to reach its fundamental limits, micro-electro-mechanical (MEM) relays provide an attractive option for improvements in energy efficiency due to their low leakage and nearly ideal I-V characteristics. However, mechanical actuation of MEM relays introduces significantly more delay than traditional CMOS electrical delay. In order to mitigate this effect, custom relay circuits are designed manually to make all mechanical actuations to happen simultaneously. A Karnaugh map-based synthesis tool was attempted to automate this design process. However, this synthesis tool has computational complexity growing exponentially in terms of the number of inputs, making it impractical for larger combinational circuit. Therefore, a synthesis algorithm based on binary decision diagram (BDD) has been investigated and developed in this work to conquer the computational complexity issue. Optimizations are performed at BDD level to reduce the number of devices needed in the design. In addition, circuits with multiple mechanical delays can also be generated by using BDD decomposition algorithm. The output is a relay netlist which can be ported to commercial place and route tools creating a simple automated MEM relay circuit design flow.