Download or read book Design of Low Power Coarse Grained Reconfigurable Architectures written by Yoonjin Kim and published by CRC Press. This book was released on 2010-12-09 with total page 215 pages. Available in PDF, EPUB and Kindle. Book excerpt: Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architect

Download or read book Designing Cost effective Coarse grained Reconfigurable Architecture written by Yoonjin Kim and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Application-specific optimization of embedded systems becomes inevitable to satisfy the market demand for designers to meet tighter constraints on cost, performance and power. On the other hand, the flexibility of a system is also important to accommodate the short time-to-market requirements for embedded systems. To compromise these incompatible demands, coarse-grained reconfigurable architecture (CGRA) has emerged as a suitable solution. A typical CGRA requires many processing elements (PEs) and a configuration cache for reconfiguration of its PE array. However, such a structure consumes significant area and power. Therefore, designing cost-effective CGRA has been a serious concern for reliability of CGRA-based embedded systems. As an effort to provide such cost-effective design, the first half of this work focuses on reducing power in the configuration cache. For power saving in the configuration cache, a low power reconfiguration technique is presented based on reusable context pipelining achieved by merging the concept of context reuse into context pipelining. In addition, we propose dynamic context compression capable of supporting only required bits of the context words set to enable and the redundant bits set to disable. Finally, we provide dynamic context management capable of reducing reduce power consumption in configuration cache by controlling a read/write operation of the redundant context words In the second part of this dissertation, we focus on designing a cost-effective PE array to reduce area and power. For area and power saving in a PE array, we devise a costeffective array fabric addresses novel rearrangement of processing elements and their interconnection designs to reduce area and power consumption. In addition, hierarchical reconfigurable computing arrays are proposed consisting of two reconfigurable computing blocks with two types of communication structure together. The two computing blocks have shared critical resources and such a sharing structure provides efficient communication interface between them with reducing overall area. Based on the proposed design approaches, a CGRA combining the multiple design schemes is shown to verify the synergy effect of the integrated approach. Experimental results show that the integrated approach reduces area by 23.07% and power by up to 72% when compared with the conventional CGRA.

Download or read book Fine and Coarse Grain Reconfigurable Computing written by Stamatis Vassiliadis and published by Springer Science & Business Media. This book was released on 2007-10-12 with total page 389 pages. Available in PDF, EPUB and Kindle. Book excerpt: Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES and DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors.

Download or read book Blocks Towards Energy efficient Coarse grained Reconfigurable Architectures written by Mark Wijtvliet and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model.

Download or read book VLSI Design and Test for Systems Dependability written by Shojiro Asai and published by Springer. This book was released on 2018-07-20 with total page 800 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book discusses the new roles that the VLSI (very-large-scale integration of semiconductor circuits) is taking for the safe, secure, and dependable design and operation of electronic systems. The book consists of three parts. Part I, as a general introduction to this vital topic, describes how electronic systems are designed and tested with particular emphasis on dependability engineering, where the simultaneous assessment of the detrimental outcome of failures and cost of their containment is made. This section also describes the related research project “Dependable VLSI Systems,” in which the editor and authors of the book were involved for 8 years. Part II addresses various threats to the dependability of VLSIs as key systems components, including time-dependent degradations, variations in device characteristics, ionizing radiation, electromagnetic interference, design errors, and tampering, with discussion of technologies to counter those threats. Part III elaborates on the design and test technologies for dependability in such applications as control of robots and vehicles, data processing, and storage in a cloud environment and heterogeneous wireless telecommunications. This book is intended to be used as a reference for engineers who work on the design and testing of VLSI systems with particular attention to dependability. It can be used as a textbook in graduate courses as well. Readers interested in dependable systems from social and industrial–economic perspectives will also benefit from the discussions in this book.

Download or read book Reconfigurable and Adaptive Computing written by Nadia Nedjah and published by CRC Press. This book was released on 2018-10-09 with total page 222 pages. Available in PDF, EPUB and Kindle. Book excerpt: Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems. The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators. The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies. The final section addresses the methodology of system codesign. The book introduces a new software–hardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task software–hardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.

Download or read book Invasive Tightly Coupled Processor Arrays written by VAHID LARI and published by Springer. This book was released on 2016-07-08 with total page 165 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

Download or read book Architectures and Tools for Efficient Reconfigurable Computing written by Stephen Chin and published by . This book was released on 2018 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Recent decades have seen large growth in the silicon industry with transistor scaling and transistor count approximately doubling every two years. With the continued growth of transistors-per-chip and increasing power density, dark silicon challenges have risen. Reconfigurable computing poses a possible solution to some of the challenges through improving performance and energy efficiency by tailoring the hardware to the application. Field-Programmable Gate Arrays (FPGAs) are a platform for realizing reconfigurable computing and have had traction for over a decade. Their recent introduction into mainstream data-centres bodes well for the field. Another type of reconfigurable architecture, Coarse Grained Reconfigurable Arrays (CGRAs), poses one other platform for computing. Being more specialized than FPGAs, CGRAs' main selling point is increased efficiency versus FPGAs, at the cost of platform flexibility. This dissertation looks at efficient computing first from the perspective of FPGAs, developing new architectures and new CAD tools, making for a more efficient FPGA. The proposed FPGA architecture consists of a hybrid multiplexer / look-up-table logic block that has reduced area with respect to traditional architectures. Then, with the prospect that CGRA architectures hold, we develop an open-source framework, CGRA-ME, for the modelling and exploration of CGRAs. This unifying software framework incorporates, architecture description through a custom language, architecture modelling, application mapping, and RTL generation, and allows further development of CGRA architectures and related CAD tools throughout the research community. Within the CGRA-ME framework, a new architecture-agnostic application mapper formulated in an integer linear program was also developed for generic CGRAs. Through this dissertation, we have made headway towards more efficient reconfigurable architectures through architecture design and related CAD and are optimistic that these contributions will have positive impact on further research and industrial application of reconfigurable architectures.

Download or read book Blocks Towards Energy efficient Coarse grained Reconfigurable Architectures written by Mark Wijtvliet and published by Springer Nature. This book was released on 2021-08-02 with total page 225 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals.

Download or read book Fine and Coarse Grain Reconfigurable Computing written by Stamatis Vassiliadis and published by Springer Science & Business Media. This book was released on 2007-09-24 with total page 389 pages. Available in PDF, EPUB and Kindle. Book excerpt: The basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures are discussed in this book. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described.

Download or read book Design of Cost Efficient Interconnect Processing Units written by Marcello Coppola and published by CRC Press. This book was released on 2020-10-14 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: Streamlined Design Solutions Specifically for NoC To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques. A Balanced Analysis of NoC Architecture As the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: how the SoC and NoC technology works why developers designed it the way they did the system-level design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and system-level networks From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors – all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.

Download or read book Adaptive Signal Processing in Wireless Communications written by Mohamed Ibnkahla and published by CRC Press. This book was released on 2017-12-19 with total page 520 pages. Available in PDF, EPUB and Kindle. Book excerpt: Adaptive techniques play a key role in modern wireless communication systems. The concept of adaptation is emphasized in the Adaptation in Wireless Communications Series through a unified framework across all layers of the wireless protocol stack ranging from the physical layer to the application layer, and from cellular systems to next-generation wireless networks. This specific volume, Adaptive Signal Processing in Wireless Communications is devoted to adaptation in the physical layer. It gives an in-depth survey of adaptive signal processing techniques used in current and future generations of wireless communication systems. Featuring the work of leading international experts, it covers adaptive channel modeling, identification and equalization, adaptive modulation and coding, adaptive multiple-input-multiple-output (MIMO) systems, and cooperative diversity. It also addresses other important aspects of adaptation in wireless communications such as hardware implementation, reconfigurable processing, and cognitive radio. A second volume in the series, Adaptation and Cross-layer Design in Wireless Networks(cat no.46039) is devoted to adaptation in the data link, network, and application layers.

Download or read book Reconfigurable Computing Architectures Tools and Applications written by Pedro C. Diniz and published by Springer. This book was released on 2007-06-04 with total page 405 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications.

Download or read book Design of Reconfigurable Hardware Architectures for Real time Applications written by Thomas Lenart and published by Thomas Lenart. This book was released on 2008 with total page 196 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Reconfigurable Embedded Control Systems Applications for Flexibility and Agility written by Khalgui, Mohamed and published by IGI Global. This book was released on 2010-11-30 with total page 652 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This book addresses the development of reconfigurable embedded control systems and describes various problems in this important research area, which include static and dynamic (manual or automatic) reconfigurations, multi-agent architectures, modeling and verification, component-based approaches, architecture description languages, distributed reconfigurable architectures, real-time and low power scheduling, execution models, and the implementation of such systems"--

Download or read book Dependable Computing Systems written by Hassan B. Diab and published by John Wiley & Sons. This book was released on 2005-10-05 with total page 693 pages. Available in PDF, EPUB and Kindle. Book excerpt: A team of recognized experts leads the way to dependable computing systems With computers and networks pervading every aspect of daily life, there is an ever-growing demand for dependability. In this unique resource, researchers and organizations will find the tools needed to identify and engage state-of-the-art approaches used for the specification, design, and assessment of dependable computer systems. The first part of the book addresses models and paradigms of dependable computing, and the second part deals with enabling technologies and applications. Tough issues in creating dependable computing systems are also tackled, including: * Verification techniques * Model-based evaluation * Adjudication and data fusion * Robust communications primitives * Fault tolerance * Middleware * Grid security * Dependability in IBM mainframes * Embedded software * Real-time systems Each chapter of this contributed work has been authored by a recognized expert. This is an excellent textbook for graduate and advanced undergraduate students in electrical engineering, computer engineering, and computer science, as well as a must-have reference that will help engineers, programmers, and technologists develop systems that are secure and reliable.

Download or read book SOC Design Methodologies written by Michel Robert and published by Springer. This book was released on 2013-03-15 with total page 489 pages. Available in PDF, EPUB and Kindle. Book excerpt: The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs & Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems. System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and integrated sensors. The complete design of such chips, in very deep submicron technologies down to 0.13 mm, with several hundreds of millions of transistors, supplied at less than 1 Volt, is a very challenging task if design, verification, debug and industrial test are considered. The microelectronic revolution is fascinating; 55 years ago, in late 1947, the transistor was invented, and everybody knows that it was by William Shockley, John Bardeen and Walter H. Brattein, Bell Telephone Laboratories, which received the Nobel Prize in Physics in 1956. Probably, everybody thinks that it was recognized immediately as a major invention.