Download or read book Cost Effective Soft Error Mitigation in Microprocessors written by Nicholas J. Wang and published by ProQuest. This book was released on 2007 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: Finally, in this work, pains were taken to include as much detail as possible in the processor model and analysis methodology. We conclude with an examination of how making various approximations in the model and analysis methodology affect the experimental results and conclusions of this and other processor reliability studies.
Download or read book Architecture Design for Soft Errors written by Shubu Mukherjee and published by Morgan Kaufmann. This book was released on 2011-08-29 with total page 361 pages. Available in PDF, EPUB and Kindle. Book excerpt: Architecture Design for Soft Errors provides a comprehensive description of the architectural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem definition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. There are a number of different ways this book can be read or used in a course: as a complete course on architecture design for soft errors covering the entire book; a short course on architecture design for soft errors; and as a reference book on classical fault-tolerant machines. This book is recommended for practitioners in semi-conductor industry, researchers and developers in computer architecture, advanced graduate seminar courses on soft errors, and (iv) as a reference book for undergraduate courses in computer architecture. Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors Shows readers how to quantify their soft error reliability Provides state-of-the-art techniques to protect against soft errors
Download or read book Soft Error Mitigation Techniques for Future Chip Multiprocessors written by Gaurang R. Upasani and published by . This book was released on 2016 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for next-generation designs. Following Moore's law, the exponential growth in the number of transistors per chip has brought tremendous progress in the performance and functionality of processors. However, incorporating billions of transistors into a chip makes it more likely to encounter a soft soft errors. Moreover, aggressive voltage scaling and process variations make the processors even more vulnerable to soft errors. Also, the number of cores on chip is growing exponentially fueling the multicore revolution. With increased core counts and larger memory arrays, the total failure-in-time (FIT) per chip (or package) increases. Our studies concluded that the shrinking technology required to match the power and performance demands for servers and future exa- and tera-scale systems impacts the FIT budget. New soft error mitigation techniques that allow meeting the failure rate target are important to keep harnessing the benefits of Moore's law. Traditionally, reliability research has focused on providing circuit, microarchitecture and architectural solutions, which include device hardening, redundant execution, lock-step, error correcting codes, modular redundancy etc. In general, all these techniques are very effective in handling soft errors but expensive in terms of performance, power, and area overheads. Traditional solutions fail to scale in providing the required degree of reliability with increasing failure rates while maintaining low area, power and performance cost. Moreover, this family of solutions has hit the point of diminishing return, and simply achieving 2X improvement in the soft error rate may be impractical. Instead of relying on some kind of redundancy, a new direction that is growing in interest by the research community is detecting the actual particle strike rather than its consequence. The proposed idea consists of deploying a set of detectors on silicon that would be in charge of perceiving the particle strikes that can potentially create a soft error. Upon detection, a hardware or software mechanism would trigger the appropriate recovery action. This work proposes a lightweight and scalable soft error mitigation solution. As a part of our soft error mitigation technique, we show how to use acoustic wave detectors for detecting and locating particle strikes. We use them to protect both the logic and the memory arrays, acting as unified error detection mechanism. We architect an error containment mechanism and a unique recovery mechanism based on checkpointing that works with acoustic wave detectors to effectively recover from soft errors. Our results show that the proposed mechanism protects the whole processor (logic, flip-flop, latches and memory arrays) incurring minimum overheads.
Download or read book Soft Errors in Modern Electronic Systems written by Michael Nicolaidis and published by Springer Science & Business Media. This book was released on 2010-09-24 with total page 331 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a comprehensive presentation of the most advanced research results and technological developments enabling understanding, qualifying and mitigating the soft errors effect in advanced electronics, including the fundamental physical mechanisms of radiation induced soft errors, the various steps that lead to a system failure, the modelling and simulation of soft error at various levels (including physical, electrical, netlist, event driven, RTL, and system level modelling and simulation), hardware fault injection, accelerated radiation testing and natural environment testing, soft error oriented test structures, process-level, device-level, cell-level, circuit-level, architectural-level, software level and system level soft error mitigation techniques. The book contains a comprehensive presentation of most recent advances on understanding, qualifying and mitigating the soft error effect in advanced electronic systems, presented by academia and industry experts in reliability, fault tolerance, EDA, processor, SoC and system design, and in particular, experts from industries that have faced the soft error impact in terms of product reliability and related business issues and were in the forefront of the countermeasures taken by these companies at multiple levels in order to mitigate the soft error effects at a cost acceptable for commercial products. In a fast moving field, where the impact on ground level electronics is very recent and its severity is steadily increasing at each new process node, impacting one after another various industry sectors (as an example, the Automotive Electronics Council comes to publish qualification requirements on soft errors), research and technology developments and industrial practices have evolve very fast, outdating the most recent books edited at 2004.
Download or read book Soft Error Reliability Using Virtual Platforms written by Felipe Rocha da Rosa and published by Springer Nature. This book was released on 2020-11-02 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes the benefits and drawbacks inherent in the use of virtual platforms (VPs) to perform fast and early soft error assessment of multicore systems. The authors show that VPs provide engineers with appropriate means to investigate new and more efficient fault injection and mitigation techniques. Coverage also includes the use of machine learning techniques (e.g., linear regression) to speed-up the soft error evaluation process by pinpointing parameters (e.g., architectural) with the most substantial impact on the software stack dependability. This book provides valuable information and insight through more than 3 million individual scenarios and 2 million simulation-hours. Further, this book explores machine learning techniques usage to navigate large fault injection datasets.
Download or read book Soft error Mitigation at the Architecture level Using Berger Codes for Error Detection written by Edward John Ossi and published by . This book was released on 2011 with total page 54 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource Constrained IoT Edge Devices written by Geancarlo Abich and published by Springer Nature. This book was released on 2023-01-01 with total page 143 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes an extensive and consistent soft error assessment of convolutional neural network (CNN) models from different domains through more than 14.8 million fault injections, considering different precision bit-width configurations, optimization parameters, and processor models. The authors also evaluate the relative performance, memory utilization, and soft error reliability trade-offs analysis of different CNN models considering a compiler-based technique w.r.t. traditional redundancy approaches.
Download or read book Euro Par 2011 Parallel Processing Workshops written by Michael Alexander and published by Springer. This book was released on 2012-04-14 with total page 502 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes thoroughly refereed post-conference proceedings of the workshops of the 17th International Conference on Parallel Computing, Euro-Par 2011, held in Bordeaux, France, in August 2011. The papers of these 12 workshops CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS HPCF, PROPER, CCPI, and VHPC focus on promotion and advancement of all aspects of parallel and distributed computing.
Download or read book Dissertation Abstracts International written by and published by . This book was released on 2008 with total page 946 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Long Term Reliability of Nanometer VLSI Systems written by Sheldon Tan and published by Springer Nature. This book was released on 2019-09-12 with total page 460 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides readers with a detailed reference regarding two of the most important long-term reliability and aging effects on nanometer integrated systems, electromigrations (EM) for interconnect and biased temperature instability (BTI) for CMOS devices. The authors discuss in detail recent developments in the modeling, analysis and optimization of the reliability effects from EM and BTI induced failures at the circuit, architecture and system levels of abstraction. Readers will benefit from a focus on topics such as recently developed, physics-based EM modeling, EM modeling for multi-segment wires, new EM-aware power grid analysis, and system level EM-induced reliability optimization and management techniques. Reviews classic Electromigration (EM) models, as well as existing EM failure models and discusses the limitations of those models; Introduces a dynamic EM model to address transient stress evolution, in which wires are stressed under time-varying current flows, and the EM recovery effects. Also includes new, parameterized equivalent DC current based EM models to address the recovery and transient effects; Presents a cross-layer approach to transistor aging modeling, analysis and mitigation, spanning multiple abstraction levels; Equips readers for EM-induced dynamic reliability management and energy or lifetime optimization techniques, for many-core dark silicon microprocessors, embedded systems, lower power many-core processors and datacenters.
Download or read book Reliable and Energy Efficient Streaming Multiprocessor Systems written by Anup Kumar Das and published by Springer. This book was released on 2018-01-03 with total page 158 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book discusses analysis, design and optimization techniques for streaming multiprocessor systems, while satisfying a given area, performance, and energy budget. The authors describe design flows for both application-specific and general purpose streaming systems. Coverage also includes the use of machine learning for thermal optimization at run-time, when an application is being executed. The design flow described in this book extends to thermal and energy optimization with multiple applications running sequentially and concurrently.
Download or read book Advances in Wireless Mobile Networks and Applications written by Salah S. Al-Majeed and published by Springer Science & Business Media. This book was released on 2011-05-10 with total page 329 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Third International Conference on Wireless, Mobile Networks and Applications, WiMoA 2011, and the First International Conference on Computer Science, Engineering and Applications, ICCSEA 2011, held in Dubai, United Arab Emirates, in May 2011. The book is organized as a collection of papers from WiMoA 2011 and ICCSEA 2011. The 8 revised full papers presented in the WiMoA 2011 part were carefully reviewed and selected from 63 submissions. The 20 revised full papers presented in the ICCSEA 2011 part were carefully reviewed and selected from 110 submissions.
Download or read book FPGAs and Parallel Architectures for Aerospace Applications written by Fernanda Kastensmidt and published by Springer. This book was released on 2015-12-07 with total page 319 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces the concepts of soft errors in FPGAs, as well as the motivation for using commercial, off-the-shelf (COTS) FPGAs in mission-critical and remote applications, such as aerospace. The authors describe the effects of radiation in FPGAs, present a large set of soft-error mitigation techniques that can be applied in these circuits, as well as methods for qualifying these circuits under radiation. Coverage includes radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.
Download or read book Approximate Computing written by Weiqiang Liu and published by Springer Nature. This book was released on 2022-08-22 with total page 607 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores the technological developments at various levels of abstraction, of the new paradigm of approximate computing. The authors describe in a single-source the state-of-the-art, covering the entire spectrum of research activities in approximate computing, bridging device, circuit, architecture, and system levels. Content includes tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and applications developed in approximate computing for a wide scope of readership and specialists. Serves as a single-source reference to state-of-the-art of approximate computing; Covers broad range of topics, from circuits to applications; Includes contributions by leading researchers, from academia and industry.
Download or read book Efficient Modeling of Soft Error Vulnerability in Microprocessors written by Arun Arvind Nair and published by . This book was released on 2012 with total page 300 pages. Available in PDF, EPUB and Kindle. Book excerpt: Reliability has emerged as a first class design concern, as a result of an exponential increase in the number of transistors on the chip, and lowering of operating and threshold voltages with each new process generation. Radiation-induced transient faults are a significant source of soft errors in current and future process generations. Techniques to mitigate their effect come at a significant cost of area, power, performance, and design effort. Architectural Vulnerability Factor (AVF) modeling has been proposed to easily estimate the processor's soft error rates, and to enable the designers to make appropriate cost/reliability trade-offs early in the design cycle. Using cycle-accurate microarchitectural or logic gate-level simulations, AVF modeling captures the masking effect of program execution on the visibility of soft errors at the output. AVF modeling is used to identify structures in the processor that have the highest contribution to the overall Soft Error Rate (SER) while running typical workloads, and used to guide the design of SER mitigation mechanisms. The precise mechanisms of interaction between the workload and the microarchitecture that together determine the overall AVF is not well studied in literature, beyond qualitative analyses. Consequently, there is no known methodology for ensuring that the workload suite used for AVF modeling offers sufficient SER coverage. Additionally, owing to the lack of an intuitive model, AVF modeling is reliant on detailed microarchitectural simulations for understanding the impact of scaling processor structures, or design space exploration studies. Microarchitectural simulations are time-consuming, and do not easily provide insight into the mechanisms of interactions between the workload and the microarchitecture to determine AVF, beyond aggregate statistics. These aforementioned challenges are addressed in this dissertation by developing two methodologies. First, beginning with a systematic analysis of the factors affecting the occupancy of corruptible state in a processor, a methodology is developed that generates a synthetic workload for a given microarchitecture such that the SER is maximized. As it is impossible for every bit in the processor to simultaneously contain corruptible state, the worst-case realizable SER while running a workload is less than the sum of their circuit-level fault rates. The knowledge of the worst-case SER enables efficient design trade-offs by allowing the architect to validate the coverage of the workload suite and select an appropriate design point, and to identify structures that may potentially have high contribution to SER. The methodology induces 1.4X higher SER in the core as compared to the highest SER induced by SPEC CPU2006 and MiBench programs. Second, a first-order analytical model is proposed, which is developed from the first principles of out-of-order superscalar execution that models the AVF induced by a workload in microarchitectural structures, using inexpensive profiling. The central component of this model is a methodology to estimate the occupancy of correct-path state in various structures in the core. Owing to its construction, the model provides fundamental insight into the precise mechanism of interaction between the workload and the microarchitecture to determine AVF. The model is used to cheaply perform sizing studies for structures in the core, design space exploration, and workload characterization for AVF. The model is used to quantitatively explain results that may appear counter-intuitive from aggregate performance metrics. The Mean Absolute Error in determining AVF of a 4-wide out-of-order superscalar processor using model is less than 7% for each structure, and the Normalized Mean Square Error for determining overall SER is 9.0%, as compared to cycle-accurate microarchitectural simulation.
Download or read book Efficient Techniques for Modeling and Mitigation of Soft Errors in Nanometer scale Static CMOS Logic Circuits written by Srivathsan Krishnamohan and published by . This book was released on 2005 with total page 282 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Dependable Computing written by Carlos Alberto Maziero and published by Springer. This book was released on 2005-10-13 with total page 279 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Second Latin-American Symposium on Dependable Computing, LADC 2005, held in Salvador, Brazil, in October 2005. The 16 revised full papers presented together with 3 invited talks, and outlines of 2 workshops and 3 tutorials, were carefully reviewed and selected from 39 submissions. The papers are organized in topical sections on evaluation, certification, modelling, embedded systems, time, and distributed systems algorithms.
