Download or read book Cache Coherence Techniques for Multicore Processors written by Michael R. Marty and published by . This book was released on 2008 with total page 232 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Primer on Memory Consistency and Cache Coherence written by Daniel Sorin and published by Morgan & Claypool Publishers. This book was released on 2011-03-02 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies

Download or read book Cache Coherence Strategies in a Many core Processor written by Christopher P. Celio and published by . This book was released on 2009 with total page 55 pages. Available in PDF, EPUB and Kindle. Book excerpt: Caches are frequently employed in memory systems, exploiting memory locality to gain advantages in high-speed performance and low latency. However, as computer processor core counts increase, maintaining coherence between caches becomes increasingly difficult. Current methods of cache coherence work well in small-scale multi-core processors, however, the viability of cache coherence as processors scale to thousands of cores remains an open question. A novel many-core execution-driven performance simulator, called Graphite and implemented by the Carbon group, has been utilized to study a variety of cache coherency strategies of processors up to 256 cores. Results suggest that cache coherence may be possible in future many-core processors, but that software developers will have to exercise great care to match their algorithms to the target architecture to avoid sub-optimal performance.

Download or read book Multi Core Cache Hierarchies written by Rajeev Balasubramonian and published by Morgan & Claypool Publishers. This book was released on 2011-06-06 with total page 155 pages. Available in PDF, EPUB and Kindle. Book excerpt: A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks

Download or read book Locality aware Cache Hierarchy Management for Multicore Processors written by and published by . This book was released on 2015 with total page 194 pages. Available in PDF, EPUB and Kindle. Book excerpt: Next generation multicore processors and applications will operate on massive data with significant sharing. A major challenge in their implementation is the storage requirement for tracking the sharers of data. The bit overhead for such storage scales quadratically with the number of cores in conventional directory-based cache coherence protocols. Another major challenge is limited cache capacity and the data movement incurred by conventional cache hierarchy organizations when dealing with massive data scales. These two factors impact memory access latency and energy consumption adversely. This thesis proposes scalable efficient mechanisms that improve effective cache capacity (i.e., by improving utilization) and reduce data movement by exploiting locality and controlling replication. First, a limited directory-based protocol, ACKwise is proposed to track the sharers of data in a cost-effective manner. ACKwise leverages broadcasts to implement scalable cache coherence. Broadcast support can be implemented in a 2-D mesh network by making simple changes to its routing policy without requiring any additional virtual channels. Second, a locality-aware replication scheme that better manages the private caches is proposed. This scheme controls replication based on data reuse information and seamlessly adapts between private and logically shared caching of on-chip data at the fine granularity of cache lines. A low-overhead runtime profiling capability to measure the locality of each cache line is built into hardware. Private caching is only allowed for data blocks with high spatio-temporal locality. Third, a Timestamp-based memory ordering validation scheme is proposed that enables the locality-aware private cache replication scheme to be implementable in processors with out-of-order memory that employ popular memory consistency models. This method does not rely on cache coherence messages to detect speculation violations, and hence is applicable to the locality-aware protocol. The timestamp mechanism is efficient due to the observation that consistency violations only occur due to conflicting accesses that have temporal proximity (i.e., within a few cycles of each other), thus requiring timestamps to be stored only for a small time window. Fourth, a locality-aware last-level cache (LLC) replication scheme that better manages the LLC is proposed. This scheme adapts replication at runtime based on fine-grained cache line reuse information and thereby, balances data locality and off-chip miss rate for optimized execution. Finally, all the above schemes are combined to obtain a cache hierarchy replication scheme that provides optimal data locality and miss rates at all levels of the cache hierarchy. The design of this scheme is motivated by the experimental observation that both locality-aware private cache & LLC replication enable varying performance improvements across benchmarks. These techniques enable optimal use of the on-chip cache capacity, and provide low-latency, low-energy memory access, while retaining the convenience of shared memory and preserving the same memory consistency model. On a 64-core multicore processor with out-of-order cores, Locality-aware Cache Hierarchy Replication improves completion time by 15% and energy by 22% over a state-of-the-art baseline while incurring a storage overhead of 30.7 KB per core. (i.e., 10% the aggregate cache capacity of each core).

Download or read book A Primer on Memory Consistency and Cache Coherence written by Vijay Nagarajan and published by Morgan & Claypool Publishers. This book was released on 2020-02-04 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Download or read book Multicore Technology written by Muhammad Yasir Qadri and published by CRC Press. This book was released on 2013-07-26 with total page 492 pages. Available in PDF, EPUB and Kindle. Book excerpt: The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing. The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debugging, and power management. This book gives readers a holistic overview of the field and guides them to further avenues of research by covering the state of the art in this area. It includes contributions from industry as well as academia.

Download or read book The Cache Coherence Problem in Shared Memory Multiprocessors written by Igor Tartalja and published by Wiley-IEEE Computer Society Press. This book was released on 1996-02-13 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book illustrates state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and details static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies.

Download or read book A Primer on Memory Consistency and Cache Coherence Second Edition written by Vijay Nagarajan and published by Springer Nature. This book was released on 2022-05-31 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Download or read book Architecture and Compiler Support for Parallel Consistency Coherence and Security written by Rui Zhang (Ph. D. in computer science) and published by . This book was released on 2020 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: The widespread use of multicore processors has made parallelism a necessity for performance. However, parallelism allows programs to share physical computing resources, such as memory and processor caches, which presents challenges for computer systems to ensure correct and secure parallel executions. Specifically, these challenges include: 1) providing strong memory consistency to programs with data races while allowing best-effort progress; 2) providing data-race-free (DRF) programs with simple, efficient cache coherence; and 3) ensuring information security for programs that run in parallel. These challenges in parallel consistency, coherence, and security motivate this work. The thesis of our work is that parallel systems can get the benefits of strong consistency, simple and efficient coherence, and strong security guarantees with little performance degradation or human effort. The goal in this dissertation is to make contributions by presenting and proposing architecture and compiler support to ensure correct and secure parallelism with minimal extra costs. Modern memory models make the DRF assumption and provide strong, well-defined end-to-end memory consistency only for DRF programs. Prior work has proposed fail-stop memory consistency to provide well-defined behaviors for all programs. However, fail-stop consistency can lead to unexpected failures in the presence of data races, imperiling performance or progress. To help systems get the benefits of fail-stop memory consistency while minimizing the costs of failures, this dissertation presents a set of architectural mechanisms that provide best-effort avoidance of failures on top of systems that provide fail-stop consistency. Unlike memory consistency models, mainstream cache coherence protocols such as MESI are designed to enforce coherence for both DRF and non-DRF programs and thus are complex. Specifically, MESI requires numerous transient states, a shared directory, and support for core-to-core communication. As DRF is widely assumed by today’s language-level memory models, this dissertation explores the possibility of providing simpler cache coherence protocols under the DRF assumption and presents a simple, efficient self-invalidation-based coherence protocol that eliminates MESI’s expensive requirements. The key insights in this work lie in its novel design that has no shared ownership metadata and that uses lightweight mechanisms to avoid many unnecessary self-invalidations. The fact that programs share physical computing resources such as memory and processor caches presents not only correctness challenges but also security threats. Among such threats, particularly worrisome are cache side-channel attacks, which have been demonstrated to be potent enough to facilitate the deduction of sensitive information in realistic scenarios. To protect programs from cache side-channel attacks, we propose automatic compiler support for strong, efficient cache side-channel protection based on widely available commodity hardware transactional memory (HTM). This work consists of a set of program analysis and instrumentation techniques that detect and analyze sensitive data and code, delimit transactions, and insert code to protect sensitive data and code. By making contributions in parallel consistency, coherence, and security, this dissertation aims to address challenges that parallelism faces to ensure correct and secure executions. Our proposed architecture support for best-effort avoidance of failures provides strong consistency without the costs of consistency failures. Our proposed coherence protocol extends the design limit of cache coherence on complexity under the DRF assumption. Last but not least, our proposed techniques of automatic cache side-channel protection help developers get the benefit of secure parallelism with little human effort. Overall, this dissertation significantly advances the state of the art in parallel consistency, coherence, and security.

Download or read book Hybrid Coherence for Scalable Multicore Architectures written by John H. Kelm and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This work describes a cache architecture and memory model for 1000+ core microprocessors. Our approach exploits workload characteristics and programming model assumptions to build a hybrid memory model that incorporates features from both software-managed coherence schemes and hardware cache coherence. The goal is to achieve the scalability found in compute accelerators, which support relaxed ordering of memory operations and programmer-managed coherence, while providing a programming interface that is akin to the strongly ordered cache coherent memory models found in general-purpose multicore processors today. The research presented in this dissertation supports the following thesis: To be scalable and programmable, future multicore systems require a cached, single-address space memory hierarchy. A hybrid software/hardware approach to coherence management is required to support such a memory hierarchy in 1000+ core processors and is achievable only by leveraging the characteristics of target applications and system software. We motivate a hybrid memory model and present our approach to addressing the challenges facing such a model. We discuss and evaluate a scalable 1024-core architecture, workloads that we see as targets for such an architecture, a memory model that relies on software management of coherence, and scalable hardware coherence schemes. Using these components, we develop the software and hardware support for a hybrid memory model. We demonstrate that our techniques can be used to reduce hardware design complexity, to increase software scalability, or to combine the two.

Download or read book Fundamentals of Parallel Multicore Architecture written by Yan Solihin and published by CRC Press. This book was released on 2015-11-18 with total page 494 pages. Available in PDF, EPUB and Kindle. Book excerpt: Although multicore is now a mainstream architecture, there are few textbooks that cover parallel multicore architectures. Filling this gap, Fundamentals of Parallel Multicore Architecture provides all the material for a graduate or senior undergraduate course that focuses on the architecture of multicore processors. The book is also useful as a ref

Download or read book Cache and Interconnect Architectures in Multiprocessors written by Michel Dubois and published by Springer. This book was released on 1990-07-31 with total page 312 pages. Available in PDF, EPUB and Kindle. Book excerpt: A collection of invited papers concerning cache coherence protocols for general interconnects. Covers the major efforts now under way to understand the architecture and performance issues of cache-based multiprocessor computer systems. Annotation copyrighted by Book News, Inc., Portland, OR

Download or read book Reducing the Area and Energy of Coherence Directories in Multicore Processors written by Jason Zebchuk and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Thread and Data Mapping for Multicore Systems written by Eduardo H. M. Cruz and published by Springer. This book was released on 2018-07-04 with total page 54 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.

Download or read book Directory Based Ring order Cache Coherence Protocol for Many core Chip Mulitprocessors written by Anup Narayan Kulkarni and published by . This book was released on 2009 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt: The success of the current trend of aggressively scaling shared-cache Chip Multi Processors (CMP) depends critically on the ability of hardware cache coherence proto¬cols to support the scaling of processing cores while providing low latency service time for cache misses. Recent research has identified the ring to be a good candidate for on-chip interconnect that supports the scaling of processor cores. An associated ring-order snoop based protocol was proposed for the ring interconnect. However, in general, snoop based protocols do not scale well for a large number of processing cores. In this thesis, we propose a variation of the ring-the hierarchical ring for shared cache CMP's. Addi¬tionally, we develop a new directory based cache coherence protocol that exploits the ring's natural round-robin order while delivering good performance in terms of reduced latency for cache misses by exploiting the shorter routes possible with the hierarchical ring. We present simulation results comparing the performance of the ring-order snoop based protocol on the hierarchical ring against our protocol using a set of synthetic benchmarks. On an average the proposed protocol has 25% lower latency than the snoop based ring-order protocol for a 128 core processor with private LI caches and a logically shared but physically distributed L2 cache.

Download or read book Architectural Techniques for Memory Oversight in Multiprocessors written by Arrvindh Shriraman and published by . This book was released on 2010 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Computer architects have exploited the transistors afforded by Moore's law to provide software developers with high performance computing resources. Software has translated this growth in hardware resources into improved features and applications. Unfortunately, applications have become increasingly complex and are prone to a variety of bugs when multiple software modules interact. The advent of multicore processors introduces a new challenge, parallel programming, which requires programmers to coordinate multiple tasks. This dissertation develops general-purpose hardware mechanisms that address the dual challenges of parallel programming and software reliability. We have devised hardware mechanisms in the memory hierarchy that shed light on the memory system and control the visibility of data among the multiple threads. The key novelty is the use of cache coherence protocols to implement hardware mechanisms that enable software to track and regulate memory accesses at cache-line granularity. We demonstrate that exposing the events in the memory hierarchy provides useful information that was either previously invisible to software or would have required heavyweight instrumentation. Focusing on the challenge of parallel programming, our mechanisms aid implementations of Transactional Memory (TM), a programming construct that seeks to simplify synchronization of shared state. We develop two mechanisms, Alert-On-Update (AOU) and Programmable Data Isolation (PDI), to accelerate common TM tasks. AOU selectively exposes cache events, including those that are triggered by remote accesses, to software in the form of events. TM runtimes use it to detect accesses that overlap between transactions (i.e., conflicts), and track a transaction's status. Programmable-Data-Isolation (PDI) allows multiple threads to temporarily hide their speculative writes from concurrent threads in their private caches until software decides to make them visible. We have used PDI and AOU to implement two TM run-time systems, RTM and FlexTM. Both RTM and FlexTM are flexible runtimes that permit software control of the timing of conflict resolution and the policy used for conflict management. To address the challenge of software reliability, we propose Sentry, a lightweight, flexible access-control mechanism. Sentry allows software to regulate the reads and writes to memory regions at cache-line granularity based on the context in the program. Sentry coordinates the coherence states in a novel manner to eliminate the need for permission checks entirely for a large majority of the program's accesses (all cache hits), thereby improving efficiency. Sentry improves application reliability by regulating data visibility and movement among the multiple software modules present in the application. We use a real-world webserver, Apache, as a case study to illustrate Sentry's ability to guard the core application from vulnerabilities in the application's modules."--Leaves vii-viii