Download or read book A Novel Test Generation Method for Small Delay Defects with User defined Fault Model written by 商朝鈞 and published by . This book was released on 2019 with total page 35 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test and Diagnosis for Small Delay Defects written by Mohammad Tehranipoor and published by Springer Science & Business Media. This book was released on 2011-09-08 with total page 228 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book will introduce new techniques for detecting and diagnosing small-delay defects in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise.
Download or read book Fault Simulation and Test Generation for Small Delay Faults written by Wangqi Qiu and published by . This book was released on 2006 with total page 130 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches.
Download or read book High Quality Transition and Small Delay Fault ATPG written by and published by . This book was released on 2004 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Path selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture small-distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. To deal with small delay faults, we have proposed a new transition fault model called As late As Possible Transition Fault (ALAPTF) Model. The model aims at detecting smaller delays, which will be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, simple path-delay model will miss such faults.
Download or read book Test Pattern Generation Techniques that Target Low Test Application Time written by Arkan M. Abdulrahman and published by . This book was released on 2008 with total page 96 pages. Available in PDF, EPUB and Kindle. Book excerpt: The dissertation investigates and proposes techniques to reduce test application time and time to market test requirements. Test generation techniques for logic and delay faults in digital circuits are presented. For logic defects, concurrent test generation in multi-core system on chip to reduce test application time is proposed. The single stuck-at fault model is considered. For timing defects, a compaction technique based on implicit path removal is proposed. The path delay fault model is considered. Also, a test generation technique for sequential (non-scan) circuits proposed.
Download or read book High Quality Test Pattern Generation and Boolean Satisfiability written by Stephan Eggersglüß and published by Springer Science & Business Media. This book was released on 2012-02-01 with total page 208 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly; Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model; Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.
Download or read book Scalable Test Generation for Path Delay Faults written by Edward Flanigan and published by . This book was released on 2009 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF), which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. The second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.
Download or read book Built in Self Test BIST for Realistic Delay Defects written by Karthik Prabhu Tamilarasan and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models.
Download or read book Optimizing Test Pattern Generation Using Top Off ATPG Methodology for Stuck AT Transition and Small Delay Defect Faults written by Arjun Singh Gill and published by . This book was released on 2013 with total page 46 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ever increasing complexity and size of digital circuits complemented by Deep Sub Micron (DSM) technology trends today pose challenges to the efficient Design For Test (DFT) methodologies. Innovation is required not only in designing the digital circuits, but also in automatic test pattern generation (ATPG) to ensure that the pattern set screens all the targeted faults while still complying with the Automatic Test Equipment (ATE) memory constraints. DSM technology trends push the requirements of ATPG to not only include the conventional static defects but also to include test patterns for dynamic defects. The current industry practices consider test pattern generation for transition faults to screen dynamic defects. It has been observed that just screening for transition faults alone is not sufficient in light of the continuing DSM technology trends. Shrinking technology nodes have pushed DFT engineers to include Small Delay Defect (SDD) test patterns in the production flow. The current industry standard ATPG tools are evolving and SDD ATPG is not the most economical option in terms of both test generation CPU time and pattern volume. New techniques must be explored in order to ensure that a quality test pattern set can be generated which includes patterns for stuck-at, transition and SDD faults, all the while ensuring that the pattern volume remains economical. This thesis explores the use of a "Top-Off" ATPG methodology to generate an optimal test pattern set which can effectively screen the required fault models while containing the pattern volume within a reasonable limit. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/149598
Download or read book High Quality Compact Delay Test Generation written by Zheng Wang and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test.
Download or read book Fault Simulation and Test Generation for Delay Faults written by Bejoy George Oomman and published by . This book was released on 1988 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book New Test Generation Methods for Transition Delay Faults in Scan Designs written by Zhuo Zhang and published by . This book was released on 2006 with total page 232 pages. Available in PDF, EPUB and Kindle. Book excerpt: The main objective of this thesis is to target the current challenges in scan based test for transition delay fault (TDF), such as yield loss, low TDF coverage as well as excessive power dissipations.
Download or read book Testing Sequence Dependent Defects written by Narendra Devta-Prasanna and published by LAP Lambert Academic Publishing. This book was released on 2009-09 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt: With new technologies that continue to shrink the feature size of integrated circuits into deep sub-micron domain, there is an increasingly higher incidence of sequence dependent defects during manufacturing. Two-pattern tests are therefore being used in manufacturing testing to supplement the traditional method of single pattern tests based on the stuck-at fault model. In this work we present methods of generating and applying two-pattern test sets to enable high quality and cost effective testing of sequence dependent defects such as transition delay faults, transistor stuck-open faults etc.
Download or read book Testing for Delay Defects Utilizing Test Data Compression Techniques written by Richard Dean Putman and published by . This book was released on 2008 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: As technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X's) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X's. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.
Download or read book Fault Simulation and Test Pattern Selectionfor Small Delay Defects Using Gpu written by 許聖章 and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Realistic Fault Modeling and Quality Test Generation of Combined Delay Faults written by Ajaykumar A. Thadhlani and published by . This book was released on 2001 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test Pattern Generation for Delay Faults written by Gerrit van Brakel and published by . This book was released on 1996 with total page 155 pages. Available in PDF, EPUB and Kindle. Book excerpt:
