Download or read book Topics in Totally Self checking Circuits and Testable CMOS Circuits written by Niraj Kumar Jha and published by . This book was released on 1985 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Totally Self Checking Circuits and Testable CMOS Circuits written by Niraj K. Jha and published by . This book was released on 1986 with total page 123 pages. Available in PDF, EPUB and Kindle. Book excerpt: A Totally Self-Checking (TSC) circuit belongs to a class of circuits used for Concurrent Error Detection (CED) purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives and error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in nMOS. Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are described. Design methods which reduce the transistor count, delay, and the number of tests of TSC checkers are also given. Another problem in the area of TSC circuits concerns embedded checkers whose inputs are not directly controllable. If they do not get all the required codewords to test them they cannot be guaranteed to be TSC. A new encoding technique and a design procedure to solve this problem are presented. It has been shown previously that the two-pattern tests used to test CMOS circuits can be invalidated by timing skews. A necessary and sufficient condition is derived to find out whether or not an AND-OR or and OR-AND CMOS realization exists for a given function so that a valid test set can always be found, even in the presence of arbitrary timing skews. A new Hybrid CMOS realization is introduced to take care of the cases in which this is not possible. Keywords: Encoding; Fault models; Self-checking circuits; and Testability.
Download or read book Testing and Reliable Design of CMOS Circuits written by Niraj K. Jha and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 239 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the last few years CMOS technology has become increas ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den sity and low power requirement. The ability to realize very com plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.
Download or read book Testable and Self checking Design of CMOS Circuits written by Manjit Singh Cheema and published by . This book was released on 1992 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Partially Self checking Circuits and Their Use in Performing Logical Operations written by Stanford University. Computer Science Department and published by . This book was released on 1973 with total page 58 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Low Power 2 of 3 Valued CMOS Self Checking Circuits written by M. Hu and published by . This book was released on 1983 with total page 6 pages. Available in PDF, EPUB and Kindle. Book excerpt: Two new schemes for the implementation of self-checking binary logic systems are proposed which utilizes low power 2-of-3-valued CMOS logic circuits. While 2-of-3-valued circuits are inherently ternary, only two of their three logic values are used in normal operation. The third (middle) logic value is used for self-checking and testing. To evaluate these circuits an open-short-conducting fault model for CMOS circuits is developed. All of the single faults in these circuits are studied and classified into four types, named mid-seeking, quasi-mid-seeking, mid-rejecting, and masked. The conclusions reached for 2-of-3-valued circuits in previous papers apply to these new circuits as well. Finally a comparison between implementation schemes is made on the basis of the size of the fault set each produces. (Author).
Download or read book On Line Testing for VLSI written by Michael Nicolaidis and published by Springer Science & Business Media. This book was released on 2013-03-09 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.
Download or read book VLSI Testing written by Stanley Leonard Hurst and published by IET. This book was released on 1998 with total page 560 pages. Available in PDF, EPUB and Kindle. Book excerpt: Hurst, an editor at the Microelectronics Journal, analyzes common problems that electronics engineers and circuit designers encounter while testing integrated circuits and the systems in which they are used, and explains a variety of solutions available for overcoming them in both digital and mixed circuits. Among his topics are faults in digital circuits, generating a digital test pattern, signatures and self-tests, structured design for testability, testing structured digital circuits and microprocessors, and financial aspects of testing. The self- contained reference is also suitable as a textbook in a formal course on the subject. Annotation copyrighted by Book News, Inc., Portland, OR
Download or read book Design of Self checking Checkers and Easily Testable Circuits written by Mohamed Abdel-Aziz Marouf and published by . This book was released on 1977 with total page 378 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1994 with total page 836 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Testing of Digital Systems written by N. K. Jha and published by Cambridge University Press. This book was released on 2003-05-08 with total page 1022 pages. Available in PDF, EPUB and Kindle. Book excerpt: Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Download or read book SOC System on a Chip Testing for Plug and Play Test Automation written by Krishnendu Chakrabarty and published by Springer Science & Business Media. This book was released on 2013-04-17 with total page 202 pages. Available in PDF, EPUB and Kindle. Book excerpt: System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.
Download or read book Integrated Circuit Test Engineering written by Ian A. Grout and published by Springer Science & Business Media. This book was released on 2005-08-22 with total page 396 pages. Available in PDF, EPUB and Kindle. Book excerpt: Using the book and the software provided with it, the reader can build his/her own tester arrangement to investigate key aspects of analog-, digital- and mixed system circuits Plan of attack based on traditional testing, circuit design and circuit manufacture allows the reader to appreciate a testing regime from the point of view of all the participating interests Worked examples based on theoretical bookwork, practical experimentation and simulation exercises teach the reader how to test circuits thoroughly and effectively
Download or read book An Introduction to Logic Circuit Testing written by Parag K. Lala and published by Morgan & Claypool Publishers. This book was released on 2009 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References
Download or read book Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits written by M. Bushnell and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 690 pages. Available in PDF, EPUB and Kindle. Book excerpt: The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
Download or read book The Design of Totally Self checking Circuits by Using Programmable Logic Arrays written by Shean Lin Wang and published by . This book was released on 1981 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Totally self checking Check Circuits for Separable Codes written by Mohammad Javad Ashjaee and published by . This book was released on 1976 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt:
