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Book Test Generation and Test Application Time Reduction for Sequential Circuits

Download or read book Test Generation and Test Application Time Reduction for Sequential Circuits written by Soo Y. Lee and published by . This book was released on 1994 with total page 252 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Delay Test Generation for Synchronous Sequential Circuits

Download or read book Delay Test Generation for Synchronous Sequential Circuits written by S. Devadas and published by . This book was released on 1989 with total page 11 pages. Available in PDF, EPUB and Kindle. Book excerpt: We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented. (RRH).

Book Combinational Test Generation for Sequential Circuits

Download or read book Combinational Test Generation for Sequential Circuits written by Yong Chang Kim and published by . This book was released on 2002 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Automatic Test Pattern Generation for Synchronous Sequential Circuits

Download or read book Automatic Test Pattern Generation for Synchronous Sequential Circuits written by Marinus Hendrik Konijnenburg and published by . This book was released on 1998 with total page 226 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Automatic Test Pattern Generator for Full Scan Sequential Circuits Using Limited Scan Operations

Download or read book Automatic Test Pattern Generator for Full Scan Sequential Circuits Using Limited Scan Operations written by Vinod Pagalone and published by . This book was released on 2006 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt: In testing sequential circuits with scan chains, the test application time is the main factor that determines the overall cost of testing the circuit. For these circuits, the test application time principally depends on the number flip-flops as well as the number of vectors in the test set. Though test set compaction is one way of reducing test application time, for a significant reduction in testing costs the duration of scan operation has to be reduced. The proposed method achieves this by using limited scan operations where the number of shifts is smaller that the actual length of the scan chain. Thus the compacted test set consists of limited scan operations in places where the scan operation cannot be dropped completely. The method uses an iterative procedure that identifies the vectors that have high fault coverage with minimal shifts in the scan chain.

Book An Automatic Test Pattern Generation Technique for Sequential Circuits Using Scan Applications

Download or read book An Automatic Test Pattern Generation Technique for Sequential Circuits Using Scan Applications written by Venkat N. Koripalli and published by . This book was released on 2006 with total page 74 pages. Available in PDF, EPUB and Kindle. Book excerpt: The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.

Book EDA for IC System Design Verification and Testing

Download or read book EDA for IC System Design Verification and Testing written by Louis Scheffer and published by CRC Press. This book was released on 2018-10-03 with total page 544 pages. Available in PDF, EPUB and Kindle. Book excerpt: Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.

Book An Approach to Test Pattern Generation for Synchronous Sequential Circuits

Download or read book An Approach to Test Pattern Generation for Synchronous Sequential Circuits written by Robert Stewart Lewis and published by . This book was released on 1967 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Journal of Information Science and Engineering

Download or read book Journal of Information Science and Engineering written by and published by . This book was released on 2000 with total page 528 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Delay Fault Testing for VLSI Circuits

Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Book Modeling the Difficulty of Automatic Test Pattern Generation for Sequential Circuits

Download or read book Modeling the Difficulty of Automatic Test Pattern Generation for Sequential Circuits written by Thomas E. Marchok and published by . This book was released on 1995 with total page 138 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Several manufacturing challenges have accompanied the explosive growth in the scale of integration for VLSI circuits. One of these is the increased difficulty of generating manufacturing test sets, which has resulted from the vast increase in the ratio of the number of transistors to the number of I/O pins. The difficulty of test generation is crucial since it impacts both the resultant product quality and time to market, both of which continue to gain importance in the present day semiconductor industry. Design for testability (DFT) techniques can be used to offset this difficulty. The mechanics of such techniques are well understood. DFT techniques are also known to increase other manufacturing costs and to decrease performance. Thus the relevant issue facing designers is not how to use DFT, but rather if such techniques should be applied. The correct decision is a matter of economics. Integrated circuit (IC) designers must balance manufacturing costs, performance, time to market, and product quality concerns. Achieving the desired balance requires the ability to quantify trade-offs in the different manufacturing costs which various DFT techniques would affect. Unfortunately, test generation cost is among the least predictable of these affected costs, even though the principal reason that DFT techniques are often applied is to reduce the difficulty of test generation. Furthermore, there does not exist a complete understanding of which circuit attributes influence the difficulty of test generation. In this thesis, a model is developed which predicts the difficulty of automatic test generation for non-scan sequential circuits. This model is based on a newly recognized circuit attribute, termed density of encoding, which differs from those notions which have been used to describe this difficulty in the past. This thesis also discusses how the concept of the density of encoding can be applied to devise more powerful sequential automatic test pattern generation algorithms, more efficient DFT techniques, and more effective synthesis for testability schemes."

Book Scientific and Technical Aerospace Reports

Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1990 with total page 244 pages. Available in PDF, EPUB and Kindle. Book excerpt: