Download or read book Rethinking the Memory Hierarchy Design with Nonvolatile Memory Technologies written by Jishen Zhao (Computer engineer) and published by . This book was released on 2014 with total page 143 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Emerging Memory Technologies written by Yuan Xie and published by Springer Science & Business Media. This book was released on 2013-10-21 with total page 321 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits.

Download or read book Exploring Memory Hierarchy Design with Emerging Memory Technologies written by Guangyu Sun and published by Springer Science & Business Media. This book was released on 2013-09-18 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.

Download or read book Durable Phase Change Memory Architectures written by and published by Academic Press. This book was released on 2020-02-21 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in Computers, Volume 118, the latest volume in this innovative series published since 1960, presents detailed coverage of new advancements in computer hardware, software, theory, design and applications. Chapters in this updated release include Introduction to non-volatile memory technologies, The emerging phase-change memory, Phase-change memory architectures, Inter-line level schemes for handling hard errors in PCMs, Handling hard errors in PCMs by using intra-line level schemes, and Addressing issues with MLC Phase-change Memory. Gives a comprehensive overlook of new memory technologies, including PCM Provides reliability features with an in-depth discussion of physical mechanisms that are currently limiting PCM capabilities Covers the work of well-known authors and researchers in the field Includes volumes that are devoted to single themes or subfields of computer science

Download or read book Phase Change Memory written by Moinuddin Khalil Ahmed Qureshi and published by Morgan & Claypool Publishers. This book was released on 2012 with total page 137 pages. Available in PDF, EPUB and Kindle. Book excerpt: As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveying the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories / Storage and System Design With Emerging Non-Volatile Memories

Download or read book Architectural Techniques to Enable Reliable and High Performance Memory Hierarchy in Chip Multi processors written by Amin Jadidi and published by . This book was released on 2018 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Constant technology scaling has enabled modern computing systems to achieve high degrees of thread-level parallelism, making the design of a highly scalable and dense memory hierarchy a major challenge. During the past few decades SRAM has been widely used as the dominant technology to build on-chip cache hierarchies. On the other hand, for the main memory, DRAM has been exploited to satisfy the applications demand. However, both of these two technologies face serious scalability and power consumption problems. While there has been enormous research work to address the drawbacks of these technologies, researchers have also been considering non-volatile memory technologies to replace SRAM and DRAM in future processors. Among dierent non-volatile technologies, Spin-Transfer Torque RAM (STT-RAM) and Phase Change Memory (PCM) are the most promising candidates to replace SRAM and DRAM technologies, respectively. Researchers believe that the memory hierarchy in future computing systems will consist of a hybrid combination of current technologies (i.e., SRAM and DRAM) and non-volatile technologies (e.g., STT-RAM, and PCM). While each of these technologies have their own unique features, they have some specic limitations as well. Therefore, in order to achieve a memory hierarchy that satises all the system-level requirements, we need to study each of these memory technologies.In this dissertation, the author proposes several mechanisms to address some of the major issues with each of these technologies. To relieve the wear-out problem in a PCM-based main memory, a compression-based platform is proposed, where the compression scheme collaborates with wear-leveling and error correction schemes to further extend the memory lifetime. On the other hand, to mitigate the write disturbance problem in PCM, a new write strategy as well as a non-overlapping data layout is proposed to manage the thermal disturbance among adjacent cells.For the on-chip cache, however, we would like to achieve a scalable low-latency conguration. To this end, the author proposes a morphable SLC-MLC STT-RAM cache which dynamically trade-os between larger capacity and lower latency, based on the applications demand. While adopting scalable memory technologies, such as STT-RAM, improves the performance of cache-sensitive applications, the cache thrashing problem will stil exist in applications with very large data working-set. To address this issue, the author proposes a selective caching mechanism for highly parallel architectures. And, also introduces a criticality-aware compressed last-level cache which is capable of holding a larger portion of the data working-set while the access latency is kept low.

Download or read book Nonvolatile Memory Design written by Hai Li and published by CRC Press. This book was released on 2017-12-19 with total page 203 pages. Available in PDF, EPUB and Kindle. Book excerpt: The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances, the authors discuss key design methodologies as well as the various functions and capabilities of the three nonvolatile memory technologies.

Download or read book Exploring the Memory Hierarchy Design with Emerging Memory Technologies written by Guangyu Sun and published by . This book was released on 2011 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Non Volatile Memory Database Management Systems written by Joy Arulraj and published by Morgan & Claypool Publishers. This book was released on 2019-02-12 with total page 193 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores the implications of non-volatile memory (NVM) for database management systems (DBMSs). The advent of NVM will fundamentally change the dichotomy between volatile memory and durable storage in DBMSs. These new NVM devices are almost as fast as volatile memory, but all writes to them are persistent even after power loss. Existing DBMSs are unable to take full advantage of this technology because their internal architectures are predicated on the assumption that memory is volatile. With NVM, many of the components of legacy DBMSs are unnecessary and will degrade the performance of data-intensive applications. We present the design and implementation of DBMS architectures that are explicitly tailored for NVM. The book focuses on three aspects of a DBMS: (1) logging and recovery, (2) storage and buffer management, and (3) indexing. First, we present a logging and recovery protocol that enables the DBMS to support near-instantaneous recovery. Second, we propose a storage engine architecture and buffer management policy that leverages the durability and byte-addressability properties of NVM to reduce data duplication and data migration. Third, the book presents the design of a range index tailored for NVM that is latch-free yet simple to implement. All together, the work described in this book illustrates that rethinking the fundamental algorithms and data structures employed in a DBMS for NVM improves performance and availability, reduces operational cost, and simplifies software development.

Download or read book Memory Hierarchy Design written by Ethan Ball and published by Createspace Independent Publishing Platform. This book was released on 2017-01-30 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt: Computer pioneers correctly predicted that programmers would want unlimited amounts of fast memory. An economical solution to that desire is a memory hierarchy, which takes advantage of locality and cost/performance of memory technologies. The principle of locality, presented in the first chapter, says that most programs do not access all code or data uniformly (see section 1.6, page 38). This principle, plus the guideline that smaller hardware is faster, led to the hierarchy based on memories of different speeds and sizes. Since fast memory is expensive, a memory hierarchy is organized into several levels-each smaller, faster, and more expensive per byte than the next level. The goal is to provide a memory system with cost almost as low as the cheapest level of memory and speed almost as fast as the fastest level. The levels of the hierarchy usually subset one another; all data in one level is also found in the level below, and all data in that lower level is found in the one below it, and so on until we reach the bottom of the hierarchy. Note that each level maps addresses from a larger memory to a smaller but faster memory higher in the hierarchy.

Download or read book Green Computing with Emerging Memory written by Takayuki Kawahara and published by Springer Science & Business Media. This book was released on 2012-05 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume describes computing innovation using non-volatile memory for a sustainable world. The text presents methods of design and implementation for non-volatile memory, allowing devices to be turned off normally when not in use, yet operate with full performance when needed.

Download or read book Non Volatile Memory Design Based On Crossbar Architecture Towards Low Power Systems and Processing In Memory written by Nicholas Jao and published by . This book was released on 2021 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: In the past 30 years, semiconductor industry and research has put forth considerable effort to scale down the field-effect transistor, driven by the trend known as Moore's Law observed in the 1970s. With every generation, advances in the silicon-based complementary metal oxide semiconductor (CMOS) become increasingly challenging as the feature size approaches the size of an atom. In the recent years, Beyond-CMOS approaches have gained considerable attention to not only find an alternative approach to transistor scaling but enable new computing paradigms and unique architectural improvements that CMOS-only platforms cannot achieve. Among the Beyond-CMOS approaches, emerging non-volatile memory (NVM) technologies show great promise for the future of memory systems. Such technologies offer high integration density, data retention under zero standby power, low cost and energy-efficient read at the expense of latency, power consumption and endurance of the write operation. Emerging NVMs offer faster speed over their mature non-volatile FLASH counterparts but cannot compete against the low cost of the density-optimized 3D vertical NAND FLASH. While emerging NVMs achieve higher integration density than existing volatile memories, their long write latency and limited write endurance makes them unsuitable to replace caches. Therefore, the applications of emerging NVM systems are limited in the existing memory hierarchy. However as emerging applications and software innovations demand high-performance computing on larger data, conventional Von Neumann systems are increasingly bottlenecked by the data movement between the physically separated memory and processing. A trend towards processing in-memory (PIM) have great potential to address the memory-intensive workloads, alleviating the repeated accesses and data movement between central processing unit (CPU) and storage. Compounded with the physical and electrical scaling limits of CMOS, these issues bring about new opportunities for novel emerging NVM designs that conventional CMOS-based memories cannot provide. One such design unique to NVMs is the crossbar architecture which enables computing in-memory by leveraging the voltage biasing at the perpendicular interconnects. This PhD thesis covers the contributions toward simulation-based exploration and modelling of crossbar structures. My dissertation work in crossbar design highlights the key insights into the device-circuit trade-offs of embedded memory design and the circuit-architecture trade-offs of computing in-memory design.

Download or read book A Primer on Memory Persistency written by Vaibhav Gogte and published by Morgan & Claypool Publishers. This book was released on 2022-02-09 with total page 115 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs. Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations. This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.

Download or read book DeNovo Rethinking the Memory Hierarchy for Disciplined Parallelism written by and published by . This book was released on 2015 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Integration of Non volatile Memory Into Storage Hierarchy written by Sheng Qiu and published by . This book was released on 2014 with total page 113 pages. Available in PDF, EPUB and Kindle. Book excerpt: In this dissertation, we present novel approaches for integrating non-volatile memory devices into storage hierarchy of a computer system. There are several types of non- volatile memory devices, such as flash memory, Phase Change Memory (PCM), Spin- transfer torque memory (STT-RAM). These devices have many appealing features for applications; however, they also offer several challenges. This dissertation is focused on how to efficiently integrate these non-volatile memories into existing memory and disk storage systems. This work is composed of two major parts. The first part investigates a main-memory system employing Phase Change Memory instead of traditional DRAM. Compared to DRAM, PCM has higher density and no static power consumption, which are very important factors for building large capacity memory systems. However, PCM has higher write latency and power consumption compared to read operations. Moreover, PCM has limited write endurance. To efficiently integrate PCM into a memory system, we have to solve the challenges brought by its expensive write operations. We propose new replacement policies and cache organizations for the last-level CPU cache, which can effectively reduce the write traffic to the PCM main memory. We evaluated our design with multiple workloads and configurations. The results show that the proposed approaches improve the lifetime and energy consumption of PCM significantly. The second part of the dissertation considers the design of a data/disk storage using non-volatile memories, e.g. flash memory, PCM and nonvolatile DIMMs. We consider multiple design options for utilizing the nonvolatile memories in the storage hierarchy. First, we consider a system that employs nonvolatile memories such as PCM or nonvolatile DIMMs on memory bus along with flash-based SSDs. We propose a hybrid file system, NVMFS, that manages both these devices. NVMFS exploits the nonvolatile memory to improve the characteristics of the write workload at the SSD. We satisfy most small random write requests on the fast nonvolatile DIMM and only do large and optimized writes on SSD. We also group data of similar update patterns together before writing to flash-SSD; as a result, we can effectively reduce the garbage collection overhead. We implemented a prototype of NVMFS in Linux and evaluated its performance through multiple benchmarks. Secondly, we consider the problem of using flash memory as a cache for a disk drive based storage system. Since SSDs are expensive, a few SSDs are designed to serve as a cache for a large number of disk drives. SSD cache space can be used for both read and write requests. In our design, we managed multiple flash-SSD devices directly at the cache layer without the help of RAID software. To ensure data reliability and cache space efficiency, we only duplicated dirty data on flash- SSDs. We also balanced the write endurance of different flash-SSDs. As a result, no single SSD will fail much earlier than the others. Thirdly, when using PCM-like devices only as data storage, it's possible to exploit memory management hardware resources to improve file system performance. However, in this case, PCM may share critical system resources such as the TLB, page table with DRAM which can potentially impact PCM's performance. To solve this problem, we proposed to employ superpages to reduce the pressure on memory management resources. As a result, the file system performance is further improved. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/151835

Download or read book Micro Architecture and Systems Support for Emerging Non Volatile Memories written by Meenakshi Sundaram Bhaskaran and published by . This book was released on 2016 with total page 127 pages. Available in PDF, EPUB and Kindle. Book excerpt: Emerging non-volatile memory technologies such as phase-change memory, resistive random access memory, spin-torque transfer memory and 3D XPoint memory promise to significantly increase the I/O sub-system performance. But, current disk-centric systems fall short in taking advantage of the bandwidth and latency characteristics of such memories. This dissertation presents three systems that address: hardware, system software and micro-architecture support for faster-than-flash non-volatile memories. First, we explore system design for using emerging non-volatile memories (NVM) as a persistent cache that bridges the price and density gap between NVMs and denser storage. Bankshot is a prototype PCIe-based intelligent cache with access latencies an order of magnitude lower than conventional SSDs. Unlike previous designs of SSD caches, Bankshot relies on the OS for heavyweight operations such as servicing misses and write-backs while allows cache hits to bypass the operating system (OS) and its associated software overhead entirely. Second, we extend the ability to define application specific interface to emerging NVM SSDs such that a broad range of applications can benefit from low-latency, high-bandwidth access to the SSD's data. Our prototype system, called Willow, supports concurrent execution of an application and trusted code within the SSD without compromising on file system protections. We present three SSD apps - Caching, Append and zero-out that showcase Willows capabilities. Caching extends Willows semantics to use the SSD storage as a persistent cache while file-append and zero-out extends the semantics for file system operations. Finally, we address the challenge of accessing byte-addressable, emerging NVMs with higher than DRAM latency when attached to the processor memory bus; specifically for loads. We propose Non-Blocking Load (NBLD), an instruction set extension to mitigate pipeline stalls from long-latency memory accesses. NBLD is a non-blocking instruction that brings data into the upper levels of the cache hierarchy, however, unlike prefetch instructions, NBLD triggers the execution of application-specific code once data is resident in the cache, effectively hiding the latency of the memory.

Download or read book The Fractal Structure of Data Reference written by Bruce McNutt and published by Springer. This book was released on 2010-12-07 with total page 133 pages. Available in PDF, EPUB and Kindle. Book excerpt: The architectural concept of a memory hierarchy has been immensely successful, making possible today's spectacular pace of technology evolution in both the volume of data and the speed of data access. Its success is difficult to understand, however, when examined within the traditional "memoryless" framework of performance analysis. The `memoryless' framework cannot properly reflect a memory hierarchy's ability to take advantage of patterns of data use that are transient. The Fractal Structure of Data Reference: Applications to the Memory Hierarchy both introduces, and justifies empirically, an alternative modeling framework in which arrivals are driven by a statistically self-similar underlying process, and are transient in nature. The substance of this book comes from the ability of the model to impose a mathematically tractable structure on important problems involving the operation and performance of a memory hierarchy. It describes events as they play out at a wide range of time scales, from the operation of file buffers and storage control cache, to a statistical view of entire disk storage applications. Striking insights are obtained about how memory hierarchies work, and how to exploit them to best advantage. The emphasis is on the practical application of such results. The Fractal Structure of Data Reference: Applications to the Memory Hierarchy will be of interest to professionals working in the area of applied computer performance and capacity planning, particularly those with a focus on disk storage. The book is also an excellent reference for those interested in database and data structure research.