Download or read book New Low Power Techniques for High Speed Wireline Receivers written by No Name Given Atharav and published by . This book was released on 2020 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the rapidly increasing Internet traffic and storage volume, the aggregate I/O bandwidth requirements in wireline systems have been climbing at a rate of approximately 2-3 times every two years. Thus, the power consumption of wireline transceivers has become increasingly more critical as higher data rates and a larger number of lanes per chip are sought. This issue is further intensified by the trade-offs between the channel loss and the power dissipation, especially in the receive path. While PAM4 signaling is attractive for lossier channels, it has mostly dictated receiver designs incorporating analog-to-digital converters (ADCs) with high power numbers. Non-return-to-zero (NRZ) receiver, on the other hand, can be realized in the analog domain, potentially consuming less power, but they must deal with a greater channel loss. This research introduces a 56-Gb/s NRZ receiver that draws 50 mW while exhibiting bit error rate (BER) of less than BER 10^(-12) for a channel loss of 25 dB at 28 GHz and 13.5 dB at 14 GHz. Such a receiver can compete with PAM4 counterparts and/or serve as part of 112-Gb/s systems that must also support 56-Gb/s NRZ reception. This work demonstrates a threefold improvement in the power efficiency.
Download or read book Low Power Techniques for CMOS Wireline Receivers written by Abishek Manian and published by . This book was released on 2016 with total page 130 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the ever-increasing need for high throughput from chip-to-chip I/Os, wireline transceivers are being pushed to operate at higher speeds. With the increase in data rates, the power consumption of broadband receivers has become critical in multi-lane applications like the Gigabit Ethernet. It is therefore desirable to minimize the power drawn by all of the building blocks. This work introduces a 40-Gb/s CMOS wireline receiver that advances the art by achieving a tenfold reduction in power and an efficiency of 0.35 mW/Gb/s. An innovative aspect of the proposed NRZ receiver is our "minimalist" approach, which recognizes that every additional stage in the data or clock path consumes more power and limits the bandwidth. The minimalist mentality avoids multiple stages in the front-end continuous-time linear equalizer (CTLE), quadrature oscillators in the clock and data recovery (CDR) circuit, clock or data buffers, or phase interpolation. Moreover, building blocks are shared among different functions so as to reduce the number of current paths between VDD and ground. Using charge-steering techniques extensively, the receiver contains only a few static bias currents adding up to about 6 mA. The minimalist approach also leads to a small footprint, about 110 um x 175 um, for the entire receiver, making it possible to design a multi-lane system in a small area and with short interconnects. This receiver incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer (DTLE) with 5.4-dB boost, a half-rate CDR circuit, a two-tap half-rate/quarter-rate decision-feedback equalizer, a 1:4 deserializer, and two new latch topologies. Since in recent designs, the CTLE draws significant power, this work introduces the DTLE as an efficient means of creating a high-frequency boost with only 0.3 mW. Fabricated in 45-nm CMOS technology, the receiver achieves a BER
Download or read book Design Techniques for High speed Low power Wireline Receivers written by Arash Zargaran Yazd and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Design of High speed Communication Circuits written by Ramesh Harjani and published by World Scientific. This book was released on 2006 with total page 233 pages. Available in PDF, EPUB and Kindle. Book excerpt: MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible. The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O. Contents: Achieving Analog Accuracy in Nanometer CMOS (M P Flynn et al.); Self-Induced Noise in Integrated Circuits (R Gharpurey & S Naraghi); High-Speed Oversampling Analog-to-Digital Converters (A Gharbiya et al.); Designing LC VCOs Using Capacitive Degeneration Techniques (B Jung & R Harjani); Fully Integrated Frequency Synthesizers: A Tutorial (S T Moon et al.); Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits (D J Allstot et al.); Equalizers for High-Speed Serial Links (P K Hanumolu et al.); Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation (C P Yue et al.). Readership: Technologists, scientists, and engineers in the field of high-speed communication circuits. It can also be used as a textbook for graduate and advanced undergraduate courses.
Download or read book Low power Multi Gb s Wireline Communication written by Masum Hossain and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Adaptive Receivers for High speed Wireline Links written by Dustin Dunwell and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by Springer. This book was released on 2014-09-22 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).
Download or read book High Speed and Lower Power Technologies written by Jung Han Choi and published by CRC Press. This book was released on 2018-09-03 with total page 328 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores up-to-date research trends and achievements on low-power and high-speed technologies in both electronics and optics. It offers unique insight into low-power and high-speed approaches ranging from devices, ICs, sub-systems and networks that can be exploited for future mobile devices, 5G networks, Internet of Things (IoT), and data centers. It collects heterogeneous topics in place to catch and predict future research directions of devices, circuits, subsystems, and networks for low-power and higher-speed technologies. Even it handles about artificial intelligence (AI) showing examples how AI technology can be combined with concurrent electronics. Written by top international experts in both industry and academia, the book discusses new devices, such as Si-on-chip laser, interconnections using graphenes, machine learning combined with CMOS technology, progresses of SiGe devices for higher-speed electronices for optic, co-design low-power and high-speed circuits for optical interconnect, low-power network-on-chip (NoC) router, X-ray quantum counting, and a design of low-power power amplifiers. Covers modern high-speed and low-power electronics and photonics. Discusses novel nano-devices, electronics & photonic sub-systems for high-speed and low-power systems, and many other emerging technologies like Si photonic technology, Si-on-chip laser, low-power driver for optic device, and network-on-chip router. Includes practical applications and recent results with respect to emerging low-power systems. Addresses the future perspective of silicon photonics as a low-power interconnections and communication applications.
Download or read book High Speed Devices and Circuits with THz Applications written by Jung Han Choi and published by CRC Press. This book was released on 2014-07-22 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt: Presenting the cutting-edge results of new device developments and circuit implementations, High-Speed Devices and Circuits with THz Applications covers the recent advancements of nano devices for terahertz (THz) applications and the latest high-speed data rate connectivity technologies from system design to integrated circuit (IC) design, providing relevant standard activities and technical specifications. Featuring the contributions of leading experts from industry and academia, this pivotal work: Discusses THz sensing and imaging devices based on nano devices and materials Describes silicon on insulator (SOI) multigate nanowire field-effect transistors (FETs) Explains the theory underpinning nanoscale nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs), simulation methods, and their results Explores the physics of the silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), as well as commercially available SiGe HBT devices and their applications Details aspects of THz IC design using standard silicon (Si) complementary metal-oxide-semiconductor (CMOS) devices, including experimental setups for measurements, detection methods, and more An essential text for the future of high-frequency engineering, High-Speed Devices and Circuits with THz Applications offers valuable insight into emerging technologies and product possibilities that are attractive in terms of mass production and compatibility with current manufacturing facilities.
Download or read book Design Techniques for Low power Electrical and Optical Serial Link Receivers written by Rui Bai and published by . This book was released on 2014 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt: As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links with low power consumption. First, a serial link receiver with scalable supply voltage for different data-rates for optimum energy efficiency is presented. Low-voltage operation is proven to be an effective way to reduce power consumption, but it has not been widely adopted in high-speed link design due to associated design challenges. The proposed receiver uses an injection-locked ring oscillator (ILRO) for low-power clock recovery and deskewing with wide jitter-tracking bandwidth. Optical link has become increasingly attractive due to the potential to deliver high aggregated bandwidth over longer distance compared to electrical links. The next design applies the architecture presented previously to an optical receiver in a wavelength-division modulated (WDM) link. Per-channel adaptation is built into the front-end transimpedance amplifier (TIA), which usually accounts for the highest power consumption, to enable energy optimization in the presence of prevalent variation. Built-in monitoring and controlling circuits facilitates automatic adaptation of the link. Lastly, a low-power decision-feedback equalizer (DFE) using charge-based latch is presented. Designing an equalizer for low-voltage links can be particularly challenging because it usually has the highest bandwidth among all components. The proposed DFE with charge-based latch retains the low power consumption of a dynamic latch while achieving comparable speed of power-hungry current-mode logic (CML) circuits.
Download or read book VLSI SoC Design Trends written by Andrea Calimera and published by Springer Nature. This book was released on 2021-07-14 with total page 372 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.
Download or read book Low Power Low Noise Body enabled Phase Locked Loop for Wireline and Wireless Transceivers written by Peng Liu and published by . This book was released on 2011 with total page 69 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Low Jitter Techniques for High Speed Phase Locked Loops written by Yu Zhao and published by . This book was released on 2022 with total page 80 pages. Available in PDF, EPUB and Kindle. Book excerpt: The problem of clock generation with low jitter becomes much more challenging as wireline transceivers are designed for higher data rates, e.g., 224 Gb/s. This dissertation addresses the clock generation problem and proposes both integer-N and fractional-N phase-locked loop architectures that achieve low jitter with low power consumption. This dissertation consists of two parts. We first introduce an integer-N PLL that incorporates two new techniques. A double-sampling architecture samples both the rising and falling edge of the reference clock, which improves the in-band phase noise by 3 dB. Also, a robust retiming technique is presented to reduce the phase noise of the frequency divider. Fabricated in 28 nm CMOS technology, the 19-GHz prototype achieves an rms jitter of 20.3 fs from 10 kHz to 100 MHz with a spur of -66 dBc, all at a power of 12 mW. Next, we propose a 56-GHz fractional-N PLL targeting 224-Gb/s PAM4 transmitters. The PLL employs a novel current-mode FIR filter to avoid phase and frequency detectors (PFDs) and charge pumps and to suppress the DSM quantization noise with negligible noise folding. To provide a compact solution suited to multi-lane systems, the PLL also incorporates an inductorless divide-by-8 circuit that draws 3.1 mW. Fabricated in 28-nm CMOS technology, the PLL exhibits an rms jitter of 110 fs, consumes 23 mW, and occupies an active area of 0.1 mm2.
Download or read book High Speed Optical Receivers with Integrated Photodiode in Nanoscale CMOS written by Filip Tavernier and published by Springer Science & Business Media. This book was released on 2011-06-20 with total page 231 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes the design of optical receivers that use the most economical integration technology, while enabling performance that is typically only found in very expensive devices. To achieve this, all necessary functionality, from light detection to digital output, is integrated on a single piece of silicon. All building blocks are thoroughly discussed, including photodiodes, transimpedance amplifiers, equalizers and post amplifiers.
Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by . This book was released on 2014-10-31 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wake up Receiver Based Ultra Low Power WBAN written by Maarten Lont and published by Springer. This book was released on 2016-10-01 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents the cross-layer design and optimization of wake-up receivers for wireless body area networks (WBAN), with an emphasis on low-power circuit design. This includes the analysis of medium access control (MAC) protocols, mixer-first receiver design, and implications of receiver impairments on wideband frequency-shift-keying (FSK) receivers. Readers will learn how the overall power consumption is reduced by exploiting the characteristics of body area networks. Theoretical models presented are validated with two different receiver implementations, in 90nm and 40nm CMOS technology.
Download or read book THz and Sub THz CMOS Electronics for High Speed Telecommunication written by Carl D’heer and published by Springer Nature. This book was released on with total page 417 pages. Available in PDF, EPUB and Kindle. Book excerpt:
