Download or read book Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures written by Pavan Kamal Sudheendra Poluri and published by . This book was released on 2014 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the feature size scales down to deep nanometer regimes, it has enabled the designers to fabricate chips with billions of transistors. The availability of such abundant computational resources on a single chip has made it possible to design chips with multiple computational cores, resulting in the inception of Chip Multiprocessors (CMPs). The widespread use of CMPs has resulted in a paradigm shift from computation-centric architectures to communication-centric architectures. With the continuous increase in the number of cores that can be fabricated on a single chip, communication between the cores has become a crucial factor in its overall performance. Network-on-Chip (NoC) paradigm has evolved into a standard on-chip interconnection network that can efficiently handle the strict communication requirements between the cores on a chip. The components of an NoC include routers, that facilitate routing of data between multiple cores and links that provide raw bandwidth for data traversal. While diminishing feature size has made it possible to integrate billions of transistors on a chip, the advantage of multiple cores has been marred with the waning reliability of transistors. Components of an NoC are not immune to the increasing number of hard faults and soft errors emanating due to extreme miniaturization of transistor sizes. Faults in an NoC result in significant ramifications such as isolation of healthy cores, deadlock, data corruption, packet loss and increased packet latency, all of which have a severe impact on the performance of a chip. This has stimulated the need to design resilient and fault tolerant NoCs. This thesis handles the issue of fault tolerance in NoC routers. Within the NoC router, the focus is specifically on the router pipeline that is responsible for the smooth flow of packets. In this thesis we propose two different fault tolerant architectures that can continue to operate in the presence of faults. In addition to these two architectures, we also propose a new reliability metric for evaluating soft error tolerant techniques targeted towards the control logic of the NoC router pipeline. First, we present Shield, a fault tolerant NoC router architecture that is capable of handling both hard faults and soft errors in its pipeline. Shield uses techniques such as spatial redundancy, exploitation of idle resources and bypassing a faulty resource to achieve hard fault tolerance. The use of these techniques reveals that Shield is six times more reliable than baseline-unprotected router. To handle soft errors, Shield uses selective hardening technique that includes hardening specific gates of the router pipeline to increase its soft error tolerance. To quantify soft error tolerance improvement, we propose a new metric called Soft Error Improvement Factor (SEIF) and use it to show that Shield's soft error tolerance is three times better than that of the baseline-unprotected router. Then, we present Soft Error Tolerant NoC Router (STNR), a low overhead fault tolerating NoC router architecture that can tolerate soft errors in the control logic of its pipeline. STNR achieves soft error tolerance based on the idea of dual execution, comparison and rollback. It exploits idle cycles in the router pipeline to perform redundant computation and comparison necessary for soft error detection. Upon the detection of a soft error, the pipeline is rolled back to the stage that got affected by the soft error. Salient features of STNR include high level of soft error detection, fault containment and minimum impact on latency. Simulations show that STNR has been able to detect all injected single soft errors in the router pipeline. To perform a quantitative comparison between STNR and other existing similar architectures, we propose a new reliability metric called Metric for Soft error Tolerance (MST) in this thesis. MST is unique in the aspect that it encompasses four crucial factors namely, soft error tolerance, area overhead, power overhead and pipeline latency overhead into a single metric. Analysis using MST shows that STNR provides better reliability while incurring low overhead compared to existing architectures.

Download or read book Design and Development of Reliable and Fault tolerant Network on chip Router Architecture written by Abdulaziz Alhussien and published by . This book was released on 2013 with total page 137 pages. Available in PDF, EPUB and Kindle. Book excerpt: Networks on Chip (NoC) systems have been proposed as potential solutions for the interconnect demands in multi-processor System-on-Chip (MPSoC) environments. With the increase in the number of transistors on-chip and as CMOS technology scales down to nano technology, electronic components and interconnects are vulnerable to the effects of radiation, temperature variations and fabrication defects. The reliability of interconnection networks becomes a critical design factor. This has led to the design and the development of robust and fault-tolerant architectures. This dissertation addresses some of the key challenges in designing fault-tolerant NoC systems. Fault-tolerant adaptive routing algorithms for 2D mesh NoC architectures are proposed. The new adaptive routing algorithms for NePA architecture are able to tolerate faults in links in the NoC by rerouting packets in a proper alternative direction. The required hardware and software extensions are discussed and the performance of the router design is evaluated. The performance and its hardware complexity of the router demonstrate the feasibility of providing fault-tolerance design for NoC. Moreover, deadlock and livelock situations affect the functionality and the performance of NoC platforms. Thus. this dissertation considers these challenges as well when developing routing algorithms. The routing algorithms are verified to provide low overhead performance while ensuring deadlock/livelock freedom. This dissertation also proposes fault-tolerant routing algorithms for high throughput Diagonal Mesh NePA (DMesh) NoC. The routing algorithms are optimized to achieve efficient performance and low cost overhead while maintaining the correctness and deadlock/livelock freedom. To achieve high performance computing, hundreds of cores are integrated inside a chip. As cores and interconnections run synchronously at certain frequencies, Electromagnetic Interference (EMI) becomes very high and may affect the electronic circuits and therefore generate faults. An asynchronous NoC chip that is based on delay-insistent logic is proposed. Performance evaluation has demonstrated the proposed approach as a solution to implement Globally Asynchronous/Locally synchronous (GALS) architectures.

Download or read book Network on Chip Architectures written by Chrysostomos Nicopoulos and published by Springer Science & Business Media. This book was released on 2009-09-18 with total page 237 pages. Available in PDF, EPUB and Kindle. Book excerpt: [2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel’s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

Download or read book Bio Inspired Fault Tolerant Algorithms for Network on Chip written by Muhammad Athar Javed Sethi and published by CRC Press. This book was released on 2020-03-17 with total page 158 pages. Available in PDF, EPUB and Kindle. Book excerpt: Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters. Key Features: Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples Lists fault-tolerant algorithms with detailed examples Reviews basic concepts of NoC Discusses NoC architectures developed-to-date

Download or read book Routing Algorithms in Networks on Chip written by Maurizio Palesi and published by Springer Science & Business Media. This book was released on 2013-10-22 with total page 411 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.

Download or read book Advanced Multicore Systems On Chip written by Abderazek Ben Abdallah and published by Springer. This book was released on 2017-09-10 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: From basic architecture, interconnection, and parallelization to power optimization, this book provides a comprehensive description of emerging multicore systems-on-chip (MCSoCs) hardware and software design. Highlighting both fundamentals and advanced software and hardware design, it can serve as a primary textbook for advanced courses in MCSoCs design and embedded systems. The first three chapters introduce MCSoCs architectures, present design challenges and conventional design methods, and describe in detail the main building blocks of MCSoCs. Chapters 4, 5, and 6 discuss fundamental and advanced on-chip interconnection network technologies for multi and many core SoCs, enabling readers to understand the microarchitectures for on-chip routers and network interfaces that are essential in the context of latency, area, and power constraints. With the rise of multicore and many-core systems, concurrency is becoming a major issue in the daily life of a programmer. Thus, compiler and software development tools are critical in helping programmers create high-performance software. Programmers should make sure that their parallelized program codes will not cause race condition, memory-access deadlocks, or other faults that may crash their entire systems. As such, Chapter 7 describes a novel parallelizing compiler design for high-performance computing. Chapter 8 provides a detailed investigation of power reduction techniques for MCSoCs at component and network levels. It discusses energy conservation in general hardware design, and also in embedded multicore system components, such as CPUs, disks, displays and memories. Lastly, Chapter 9 presents a real embedded MCSoCs system design targeted for health monitoring in the elderly.

Download or read book Networks on Chip written by Axel Jantsch and published by Springer Science & Business Media. This book was released on 2007-05-08 with total page 304 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

Download or read book Dependable Multicore Architectures at Nanoscale written by Marco Ottavi and published by Springer. This book was released on 2017-08-28 with total page 294 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides comprehensive coverage of the dependability challenges in today's advanced computing systems. It is an in-depth discussion of all the technological and design-level techniques that may be used to overcome these issues and analyzes various dependability-assessment methods. The impact of individual application scenarios on the definition of challenges and solutions is considered so that the designer can clearly assess the problems and adjust the solution based on the specifications in question. The book is composed of three sections, beginning with an introduction to current dependability challenges arising in complex computing systems implemented with nanoscale technologies, and of the effect of the application scenario. The second section details all the fault-tolerance techniques that are applicable in the manufacture of reliable advanced computing devices. Different levels, from technology-level fault avoidance to the use of error correcting codes and system-level checkpointing are introduced and explained as applicable to the different application scenario requirements. Finally the third section proposes a roadmap of future trends in and perspectives on the dependability and manufacturability of advanced computing systems from the special point of view of industrial stakeholders. Dependable Multicore Architectures at Nanoscale showcases the original ideas and concepts introduced into the field of nanoscale manufacturing and systems reliability over nearly four years of work within COST Action IC1103 MEDIAN, a think-tank with participants from 27 countries. Academic researchers and graduate students working in multi-core computer systems and their manufacture will find this book of interest as will industrial design and manufacturing engineers working in VLSI companies.

Download or read book Designing 2D and 3D Network on Chip Architectures written by Konstantinos Tatas and published by Springer Science & Business Media. This book was released on 2013-10-08 with total page 271 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Download or read book Algorithms and Architectures for Parallel Processing written by Guojun Wang and published by Springer. This book was released on 2015-11-16 with total page 880 pages. Available in PDF, EPUB and Kindle. Book excerpt: This four volume set LNCS 9528, 9529, 9530 and 9531 constitutes the refereed proceedings of the 15th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2015, held in Zhangjiajie, China, in November 2015. The 219 revised full papers presented together with 77 workshop papers in these four volumes were carefully reviewed and selected from 807 submissions (602 full papers and 205 workshop papers). The first volume comprises the following topics: parallel and distributed architectures; distributed and network-based computing and internet of things and cyber-physical-social computing. The second volume comprises topics such as big data and its applications and parallel and distributed algorithms. The topics of the third volume are: applications of parallel and distributed computing and service dependability and security in distributed and parallel systems. The covered topics of the fourth volume are: software systems and programming models and performance modeling and evaluation.

Download or read book Communication Architectures for Systems on Chip written by José L. Ayala and published by CRC Press. This book was released on 2018-09-03 with total page 449 pages. Available in PDF, EPUB and Kindle. Book excerpt: A presentation of state-of-the-art approaches from an industrial applications perspective, Communication Architectures for Systems-on-Chip shows professionals, researchers, and students how to attack the problem of data communication in the manufacture of SoC architectures. With its lucid illustration of current trends and research improving the performance, quality, and reliability of transactions, this is an essential reference for anyone dealing with communication mechanisms for embedded systems, systems-on-chip, and multiprocessor architectures—or trying to overcome existing limitations. Exploring architectures currently implemented in manufactured SoCs—and those being proposed—this book analyzes a wide range of applications, including: Well-established communication buses Less common networks-on-chip Modern technologies that include the use of carbon nanotubes (CNTs) Optical links used to speed up data transfer and boost both security and quality of service (QoS) The book’s contributors pay special attention to newer problems, including how to protect transactions of critical on-chip information (personal data, security keys, etc.) from an external attack. They examine mechanisms, revise communication protocols involved, and analyze overall impact on system performance.

Download or read book Multicore Systems On Chip Practical Software Hardware Design written by Abderazek Ben Abdallah and published by Springer Science & Business Media. This book was released on 2013-07-20 with total page 291 pages. Available in PDF, EPUB and Kindle. Book excerpt: System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device’s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processing cores and that load balancing between processing cores – especially heterogeneous cores – is very difficult.

Download or read book Networks on Chips written by Giovanni De Micheli and published by Elsevier. This book was released on 2006-08-30 with total page 408 pages. Available in PDF, EPUB and Kindle. Book excerpt: The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions. * Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends * An integrated presentation not currently available in any other book * A thorough introduction to current design methodologies and chips designed with NoCs

Download or read book Design and Test Strategies for 2D 3D Integration for NoC based Multicore Architectures written by Kanchan Manna and published by Springer Nature. This book was released on 2019-12-20 with total page 167 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.

Download or read book Multi Core Embedded Systems written by Georgios Kornaros and published by CRC Press. This book was released on 2018-10-08 with total page 502 pages. Available in PDF, EPUB and Kindle. Book excerpt: Details a real-world product that applies a cutting-edge multi-core architecture Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner. Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth. Discusses the available programming models spread across different abstraction levels The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as: Architectures and interconnects Embedded design methodologies Mapping of applications

Download or read book Architecture of Computing Systems ARCS 2012 written by Andreas Herkersdorf and published by Springer Science & Business Media. This book was released on 2012-02-09 with total page 264 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 25th International Conference on Architecture of Computing Systems, ARCS 2012, held in Munich, Germany, in February/March 2012. The 20 revised full papers presented in 7 technical sessions were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on robustness and fault tolerance, power-aware processing, parallel processing, processor cores, optimization, and communication and memory.

Download or read book Fault Tolerant Computer Architecture written by Daniel Sorin and published by Morgan & Claypool Publishers. This book was released on 2009-07-08 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt: For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future