Download or read book Fault Tolerant Multiprocessor Routing with Multiple Simultaneous Link Failures written by Quinn O. Snell and published by . This book was released on 1993 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Testbed for Evaluation of Fault tolerant Routing in Multiprocessor Interconnection Networks written by Aniruddha S. Vaidya and published by . This book was released on 1998 with total page 20 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "With parallel machines increasingly taking on critical and complex applications, it is important to make them dependable to ensure their commercial success. Fault-tolerance in the network to accommodate link and node failures is an important step towards this goal. This can be achieved by employing cost-effective fault-tolerant algorithms. However, despite substantial efforts on the theoretical front in developing fault-tolerant routing techniques and architectures, these ideas have not manifested themselves in many commercial platforms. The ramifications of providing fault-tolerant routing in terms of cost and performance is still not clear to the computer architect. Such an insight can only be gained through detailed analysis of a design with realistic workloads. Since no current evaluation platform supports this, previous research on fault-tolerant routing has used synthetic workloads for analyzing performance. This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance tradeoffs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures, by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults."
Download or read book Masters Theses in the Pure and Applied Sciences written by Wade H. Shafer and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 427 pages. Available in PDF, EPUB and Kindle. Book excerpt: Masters Theses in the Pure and Applied Sciences was first conceived, published, and disseminated by the Center for Information and Numerical Data Analysis and Synthesis (CINDAS)* at Purdue University in 1957, starting its coverage of theses with the academic year 1955. Beginning with Volume 13, the printing and dis semination phases of the activity were transferred to University Microfilms/Xerox of Ann Arbor, Michigan, with the thought that such an arrangement would be more beneficial to the academic and general scientific and technical community. After five years of this joint undertaking we had concluded that it was in the interest of all concerned if the printing and distribution of the volumes were handled by an international publishing house to assure improved service and broader dissemination. Hence, starting with Volume 18, Masters Theses in the Pure and Applied Sciences has been disseminated on a worldwide basis by Plenum Publishing Corporation of New York, and in the same year the coverage was broadened to include Canadian universities. All back issues can also be ordered from Plenum. We have reported in Volume 39 (thesis year 1994) a total of 13,953 thesis titles from 21 Canadian and 159 United States universities. We are sure that this broader base for these titles reported will greatly enhance the value of this impor tant annual reference work. While Volume 39 reports theses submitted in 1994, on occasion, certain uni versities do report theses submitted in previous years but not reported at the time.
Download or read book Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures written by Pavan Kamal Sudheendra Poluri and published by . This book was released on 2014 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the feature size scales down to deep nanometer regimes, it has enabled the designers to fabricate chips with billions of transistors. The availability of such abundant computational resources on a single chip has made it possible to design chips with multiple computational cores, resulting in the inception of Chip Multiprocessors (CMPs). The widespread use of CMPs has resulted in a paradigm shift from computation-centric architectures to communication-centric architectures. With the continuous increase in the number of cores that can be fabricated on a single chip, communication between the cores has become a crucial factor in its overall performance. Network-on-Chip (NoC) paradigm has evolved into a standard on-chip interconnection network that can efficiently handle the strict communication requirements between the cores on a chip. The components of an NoC include routers, that facilitate routing of data between multiple cores and links that provide raw bandwidth for data traversal. While diminishing feature size has made it possible to integrate billions of transistors on a chip, the advantage of multiple cores has been marred with the waning reliability of transistors. Components of an NoC are not immune to the increasing number of hard faults and soft errors emanating due to extreme miniaturization of transistor sizes. Faults in an NoC result in significant ramifications such as isolation of healthy cores, deadlock, data corruption, packet loss and increased packet latency, all of which have a severe impact on the performance of a chip. This has stimulated the need to design resilient and fault tolerant NoCs. This thesis handles the issue of fault tolerance in NoC routers. Within the NoC router, the focus is specifically on the router pipeline that is responsible for the smooth flow of packets. In this thesis we propose two different fault tolerant architectures that can continue to operate in the presence of faults. In addition to these two architectures, we also propose a new reliability metric for evaluating soft error tolerant techniques targeted towards the control logic of the NoC router pipeline. First, we present Shield, a fault tolerant NoC router architecture that is capable of handling both hard faults and soft errors in its pipeline. Shield uses techniques such as spatial redundancy, exploitation of idle resources and bypassing a faulty resource to achieve hard fault tolerance. The use of these techniques reveals that Shield is six times more reliable than baseline-unprotected router. To handle soft errors, Shield uses selective hardening technique that includes hardening specific gates of the router pipeline to increase its soft error tolerance. To quantify soft error tolerance improvement, we propose a new metric called Soft Error Improvement Factor (SEIF) and use it to show that Shield's soft error tolerance is three times better than that of the baseline-unprotected router. Then, we present Soft Error Tolerant NoC Router (STNR), a low overhead fault tolerating NoC router architecture that can tolerate soft errors in the control logic of its pipeline. STNR achieves soft error tolerance based on the idea of dual execution, comparison and rollback. It exploits idle cycles in the router pipeline to perform redundant computation and comparison necessary for soft error detection. Upon the detection of a soft error, the pipeline is rolled back to the stage that got affected by the soft error. Salient features of STNR include high level of soft error detection, fault containment and minimum impact on latency. Simulations show that STNR has been able to detect all injected single soft errors in the router pipeline. To perform a quantitative comparison between STNR and other existing similar architectures, we propose a new reliability metric called Metric for Soft error Tolerance (MST) in this thesis. MST is unique in the aspect that it encompasses four crucial factors namely, soft error tolerance, area overhead, power overhead and pipeline latency overhead into a single metric. Analysis using MST shows that STNR provides better reliability while incurring low overhead compared to existing architectures.
Download or read book On the Fault Tolerance of Process Allocation and Communication on Message Passing Multiprocessor Systems written by Chungti Albert Liang and published by . This book was released on 1991 with total page 388 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multipath Fault tolerant Routing Policies to Deal with Dynamic Link Failures in High Speed Interconnection Networks written by Gonzalo Zarza and published by . This book was released on 2011 with total page 177 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Design And Analysis Of Reliable And Fault tolerant Computer Systems written by Mostafa I Abd-el-barr and published by World Scientific. This book was released on 2006-12-15 with total page 463 pages. Available in PDF, EPUB and Kindle. Book excerpt: Covering both the theoretical and practical aspects of fault-tolerant mobile systems, and fault tolerance and analysis, this book tackles the current issues of reliability-based optimization of computer networks, fault-tolerant mobile systems, and fault tolerance and reliability of high speed and hierarchical networks.The book is divided into six parts to facilitate coverage of the material by course instructors and computer systems professionals. The sequence of chapters in each part ensures the gradual coverage of issues from the basics to the most recent developments. A useful set of references, including electronic sources, is listed at the end of each chapter./a
Download or read book Masters Theses in the Pure and Applied Sciences written by W. H. Shafer and published by Springer Science & Business Media. This book was released on 1994 with total page 410 pages. Available in PDF, EPUB and Kindle. Book excerpt: Volume 37 (thesis year 1992) reports a total of 12,549 thesis titles from 25 Canadian and 153 US universities (theses submitted in previous years but only now reported are indicated by the thesis year shown in parenthesis). The organization, like that of past years, consists of thesis titles arrange
Download or read book Fault Tolerance and Performance Improvement in Multiprocessor Interconnection Networks written by Krishnan Padmanabhan and published by . This book was released on 1984 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Parallel and Distributed Processing and Applications written by Yi Pan and published by Springer Science & Business Media. This book was released on 2005-10-21 with total page 1182 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Third International Symposium on Parallel and Distributed Processing and Applications, ISPA 2005, held in Nanjing, China in November 2005. The 90 revised full papers and 19 revised short papers presented together with 3 keynote speeches and 2 tutorials were carefully reviewed and selected from 645 submissions. The papers are organized in topical sections on cluster systems and applications, performance evaluation and measurements, distributed algorithms and systems, fault tolerance and reliability, high-performance computing and architecture, parallel algorithms and systems, network routing and communication algorithms, security algorithms and systems, grid applications and systems, database applications and data mining, distributed processing and architecture, sensor networks and protocols, peer-to-peer algorithms and systems, internet computing and Web technologies, network protocols and switching, and ad hoc and wireless networks.
Download or read book Advanced Computer Architecture and Parallel Processing written by Hesham El-Rewini and published by John Wiley & Sons. This book was released on 2005-04-08 with total page 288 pages. Available in PDF, EPUB and Kindle. Book excerpt: Computer architecture deals with the physical configuration, logical structure, formats, protocols, and operational sequences for processing data, controlling the configuration, and controlling the operations over a computer. It also encompasses word lengths, instruction codes, and the interrelationships among the main parts of a computer or group of computers. This two-volume set offers a comprehensive coverage of the field of computer organization and architecture.
Download or read book Master s Theses Directories written by and published by . This book was released on 1994 with total page 590 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Education, arts and social sciences, natural and technical sciences in the United States and Canada".
Download or read book Fault tolerant Design for Multistage Routing Networks written by A. DeHon and published by . This book was released on 1990 with total page 21 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the size of digital systems increases, the mean time between single component failures diminishes. To avoid component related failures, large computers must be fault-tolerant. In this paper, we focus on methods for achieving a high degree of fault-tolerance in multistage routing networks. We describe a multipath scheme for providing end-to-end fault-tolerance on large networks. The scheme improves routing performance while keeping network latency low. We also describe the novel routing component, RN1, which implements this scheme, showing how it can be the basic building block for fault-tolerant multistage routing networks.
Download or read book Efficient Fault Tolerant Routing in DeBruijn Multiprocessor Networks written by Srinivas Reddy Goli and published by . This book was released on 1993 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Advances in Microelectronics Reviews Vol 1 written by Sergey Yurish and published by Lulu.com. This book was released on 2017-12-24 with total page 536 pages. Available in PDF, EPUB and Kindle. Book excerpt: The 1st volume of 'Advances in Microelectronics: Reviews' Book Series contains 19 chapters written by 72 authors from academia and industry from 16 countries. With unique combination of information in each volume, the 'Advances in Microelectronics: Reviews' Book Series will be of value for scientists and engineers in industry and at universities. In order to offer a fast and easy reading of the state of the art of each topic, every chapter in this book is independent and self-contained. All chapters have the same structure: first an introduction to specific topic under study; second particular field description including sensing applications. Each of chapter is ending by well selected list of references with books, journals, conference proceedings and web sites. This book ensures that readers will stay at the cutting edge of the field and get the right and effective start point and road map for the further researches and developments.
Download or read book Interconnection Networks for Multiprocessors and Multicomputers written by Anujan Varma and published by . This book was released on 1994 with total page 598 pages. Available in PDF, EPUB and Kindle. Book excerpt: Computer Systems Organization -- Computer-Communication Networks.
Download or read book Networks on Chip written by Axel Jantsch and published by Springer Science & Business Media. This book was released on 2007-05-08 with total page 304 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
