Download or read book Defect Oriented Testing for CMOS Analog and Digital Circuits written by Manoj Sachdev and published by Springer Science & Business Media. This book was released on 2013-06-29 with total page 317 pages. Available in PDF, EPUB and Kindle. Book excerpt: Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal

Download or read book Defect Oriented Testing for Nano Metric CMOS VLSI Circuits written by Manoj Sachdev and published by Springer Science & Business Media. This book was released on 2007-06-04 with total page 343 pages. Available in PDF, EPUB and Kindle. Book excerpt: The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

Download or read book Integrated Circuit Test Engineering written by Ian A. Grout and published by Springer Science & Business Media. This book was released on 2005-08-22 with total page 396 pages. Available in PDF, EPUB and Kindle. Book excerpt: Using the book and the software provided with it, the reader can build his/her own tester arrangement to investigate key aspects of analog-, digital- and mixed system circuits Plan of attack based on traditional testing, circuit design and circuit manufacture allows the reader to appreciate a testing regime from the point of view of all the participating interests Worked examples based on theoretical bookwork, practical experimentation and simulation exercises teach the reader how to test circuits thoroughly and effectively

Download or read book Test and Design for Testability in Mixed Signal Integrated Circuits written by Jose Luis Huertas Díaz and published by Springer Science & Business Media. This book was released on 2010-02-23 with total page 310 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test and Design-for-Testability in Mixed-Signal Integrated Circuits deals with test and design for test of analog and mixed-signal integrated circuits. Especially in System-on-Chip (SoC), where different technologies are intertwined (analog, digital, sensors, RF); test is becoming a true bottleneck of present and future IC projects. Linking design and test in these heterogeneous systems will have a tremendous impact in terms of test time, cost and proficiency. Although it is recognized as a key issue for developing complex ICs, there is still a lack of structured references presenting the major topics in this area. The aim of this book is to present basic concepts and new ideas in a manner understandable for both professionals and students. Since this is an active research field, a comprehensive state-of-the-art overview is very valuable, introducing the main problems as well as the ways of solution that seem promising, emphasizing their basis, strengths and weaknesses. In essence, several topics are presented in detail. First of all, techniques for the efficient use of DSP-based test and CAD test tools. Standardization is another topic considered in the book, with focus on the IEEE 1149.4. Also addressed in depth is the connecting design and test by means of using high-level (behavioural) description techniques, specific examples are given. Another issue is related to test techniques for well-defined classes of integrated blocks, like data converters and phase-locked-loops. Besides these specification-driven testing techniques, fault-driven approaches are described as they offer potential solutions which are more similar to digital test methods. Finally, in Design-for-Testability and Built-In-Self-Test, two other concepts that were taken from digital design, are introduced in an analog context and illustrated for the case of integrated filters. In summary, the purpose of this book is to provide a glimpse on recent research results in the area of testing mixed-signal integrated circuits, specifically in the topics mentioned above. Much of the work reported herein has been performed within cooperative European Research Projects, in which the authors of the different chapters have actively collaborated. It is a representative snapshot of the current state-of-the-art in this emergent field.

Download or read book Test and Diagnosis of Analogue Mixed signal and RF Integrated Circuits written by Yichuang Sun and published by IET. This book was released on 2008-05-30 with total page 411 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of those areas. A complete range of circuit components are covered and test issues from the SoC perspective. An essential reference for researchers and engineers in mixed signal testing, postgraduate and senior undergraduate students.

Download or read book Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits written by M. Bushnell and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 690 pages. Available in PDF, EPUB and Kindle. Book excerpt: The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.

Download or read book Computer Aided Design of Analog Integrated Circuits and Systems written by Rob A. Rutenbar and published by John Wiley & Sons. This book was released on 2002-05-06 with total page 773 pages. Available in PDF, EPUB and Kindle. Book excerpt: The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: * Analog synthesis * Symbolic analysis * Analog layout * Analog modeling and analysis * Specialized analog simulation * Circuit centering and yield optimization * Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck.

Download or read book Power Constrained Testing of VLSI Circuits written by Nicola Nicolici and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt: This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.

Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Download or read book Testing Static Random Access Memories written by Said Hamdioui and published by Springer Science & Business Media. This book was released on 2013-06-29 with total page 231 pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.

Download or read book Analog and Mixed Signal Boundary Scan written by Adam Osseiran and published by Springer Science & Business Media. This book was released on 2013-03-09 with total page 171 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book contains more than the IEEE Standard 1149.4. It also contains the thoughts of those who developed the standard. Adam Osseiran has edited the original writings of Brian Wilkins, Colin Maunder, Rod Tulloss, Steve Sunter, Mani Soma, Keith Lofstrom and John McDermid, all of whom have personally contributed to this standard. To preserve the original spirit, only minor changes were made, and the reader will sense a chapter-to-chapter variation in the style of expression. This may appear awkward to some, although I found the Iack of monotonicity refreshing. A system consists of a specific organization of parts. The function of the system cannot be performed by an individual part or even a disorganized collection ofthe same parts. Testing has a system-like characteristic. Testing of a system does not follow directly from the testing of its parts, and a system built with testable parts can sometimes be impossible to test. Therefore, testability of the system must be organized. Some years ago, the IEEE published the boundary-scan Standard 1149.1. That Standard provided an architecture for digital VLSI chips. The chips designed with the 1149.1 architecture can be integrated into a testable system. However, many systems today contain both analog and digital chips. Even if all digital chips are compliant with the standard, the testability of a mixed-signal system cannot be guaranteed. The new Standard 1149.4, described in this book, extends the previous architecture to mixed-signal systems.

Download or read book A Designer s Guide to Built In Self Test written by Charles E. Stroud and published by Springer Science & Business Media. This book was released on 2005-12-27 with total page 338 pages. Available in PDF, EPUB and Kindle. Book excerpt: A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.

Download or read book Test Resource Partitioning for System on a Chip written by Vikram Iyengar and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 234 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic. SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume. Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.

Download or read book Boundary Scan Interconnect Diagnosis written by José T. de Sousa and published by Springer Science & Business Media. This book was released on 2005-12-28 with total page 178 pages. Available in PDF, EPUB and Kindle. Book excerpt: This pioneering text explains how to synthesize digital diagnostic sequences for wire interconnects using boundary-scan, and how to assess the quality of those sequences. It takes a new approach, carefully modelling circuit and interconnect faults, and applying graph techniques to solve problems.

Download or read book Principles of Testing Electronic Systems written by Samiha Mourad and published by John Wiley & Sons. This book was released on 2000-07-25 with total page 444 pages. Available in PDF, EPUB and Kindle. Book excerpt: A pragmatic approach to testing electronic systems As we move ahead in the electronic age, rapid changes in technology pose an ever-increasing number of challenges in testing electronic products. Many practicing engineers are involved in this arena, but few have a chance to study the field in a systematic way-learning takes place on the job. By covering the fundamental disciplines in detail, Principles of Testing Electronic Systems provides design engineers with the much-needed knowledge base. Divided into five major parts, this highly useful reference relates design and tests to the development of reliable electronic products; shows the main vehicles for design verification; examines designs that facilitate testing; and investigates how testing is applied to random logic, memories, FPGAs, and microprocessors. Finally, the last part offers coverage of advanced test solutions for today's very deep submicron designs. The authors take a phenomenological approach to the subject matter while providing readers with plenty of opportunities to explore the foundation in detail. Special features include: * An explanation of where a test belongs in the design flow * Detailed discussion of scan-path and ordering of scan-chains * BIST solutions for embedded logic and memory blocks * Test methodologies for FPGAs * A chapter on testing system on a chip * Numerous references

Download or read book High Performance Memory Testing written by R. Dean Adams and published by Springer Science & Business Media. This book was released on 2005-12-29 with total page 252 pages. Available in PDF, EPUB and Kindle. Book excerpt: Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Download or read book SOC System on a Chip Testing for Plug and Play Test Automation written by Krishnendu Chakrabarty and published by Springer Science & Business Media. This book was released on 2013-04-17 with total page 202 pages. Available in PDF, EPUB and Kindle. Book excerpt: System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.