Download or read book Cross layer Fault Tolerance in Networks on chip written by Gert Schley and published by . This book was released on 2018 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Providing Integrity in Real Time Networks on Chip written by Eberle A. Rambo and published by . This book was released on 2019 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Mixed-critical real-time systems must meet strict integrity, resilience and timing constraints, as specified by safety standards. Due to the increasing threat of random hardware faults, efficiently achieving high reliability and dependability calls for cross-layer fault-tolerance solutions. This work introduces the Advanced Integrity Q-service (AIQ), a mechanism to ensure the integrity and predictability of on-Chip communication under random hardware faults. Devised for cross-layer and hierarchical fault-tolerance solutions, AIQ realizes low-overhead error detection in hardware and delegates error handling to arbitrary strategies in software. Experimental evaluation featuring benchmark applications and an industrial avionics use case shows that AIQ operates with high reliability and availability and low hardware and performance overheads. In a many-core mixed-critical platform under expected real-time scenarios, AIQ performs with execution time overhead between 1.4% and 7.1%.
Download or read book Networks on Chip written by Axel Jantsch and published by Springer Science & Business Media. This book was released on 2007-05-08 with total page 304 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
Download or read book Asynchronous On Chip Networks and Fault Tolerant Techniques written by Wei Song and published by CRC Press. This book was released on 2022-05-10 with total page 381 pages. Available in PDF, EPUB and Kindle. Book excerpt: Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications. As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts – faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks. This book will serve as an essential guide for researchers and students studying interconnection networks, fault-tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.
Download or read book Design Space Exploration and Resource Management of Multi Many Core Systems written by Amit Kumar Singh and published by MDPI. This book was released on 2021-05-10 with total page 218 pages. Available in PDF, EPUB and Kindle. Book excerpt: The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends.
Download or read book Bio Inspired Fault Tolerant Algorithms for Network on Chip written by Muhammad Athar Javed Sethi and published by CRC Press. This book was released on 2020-03-17 with total page 212 pages. Available in PDF, EPUB and Kindle. Book excerpt: Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters. Key Features: Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples Lists fault-tolerant algorithms with detailed examples Reviews basic concepts of NoC Discusses NoC architectures developed-to-date
Download or read book Link Faults Analysis and Fault Tolerant Techniques on Network on chip System written by Ying Fei Teh and published by . This book was released on 2012 with total page 72 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Application Layer Fault Tolerance Protocols written by De Florio, Vincenzo and published by IGI Global. This book was released on 2009-01-31 with total page 378 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This book increases awareness of the need for application-level fault-tolerance (ALFT) through introduction of problems and qualitative analysis of solutions"--Provided by publisher.
Download or read book Dependable Embedded Systems written by Jörg Henkel and published by Springer Nature. This book was released on 2020-12-09 with total page 606 pages. Available in PDF, EPUB and Kindle. Book excerpt: This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems.
Download or read book Cross Layer Reliability of Computing Systems written by Giorgio Di Natale and published by Institution of Engineering and Technology. This book was released on 2020-03-28 with total page 328 pages. Available in PDF, EPUB and Kindle. Book excerpt: Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques. Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack. This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods. Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.
Download or read book Networks on Chips written by Giovanni De Micheli and published by Elsevier. This book was released on 2006-08-30 with total page 408 pages. Available in PDF, EPUB and Kindle. Book excerpt: The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.* Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends* An integrated presentation not currently available in any other book* A thorough introduction to current design methodologies and chips designed with NoCs
Download or read book Network on Chip written by Santanu Kundu and published by CRC Press. This book was released on 2018-09-03 with total page 388 pages. Available in PDF, EPUB and Kindle. Book excerpt: Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.
Download or read book Hardware and Software Fault Tolerance in Parallel Computing Systems written by Dimitri Ranguelov Avresky and published by Prentice Hall. This book was released on 1992 with total page 360 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Transient and Permanent Error Management for Networks on chip written by Qiaoyan Yu and published by . This book was released on 2011 with total page 502 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Reliability has become one of the most important metrics for on-chip communications infrastructures in nanoscale technologies. Reduced supply voltages and high clock frequency exacerbate the impact of noise sources such as particle strikes and crosstalk, which can cause transient errors in transmitted data. Manufacturing defects and aging issues can cause permanent errors in the communication links. The modularity of the Networks-on-Chip (NoCs) approach facilitates the exploration of error control techniques for on-chip interconnects and many-cores systems. Unfortunately, error control is not free. Worst-case error management methods are simple but waste energy and bandwidth in favorable noise conditions. Consequently, cost-effective techniques for improving link error resilience are needed. In this work, we propose configurable error control methods to tackle variable transient errors and exploit existing transient error control redundancy for permanent error management, achieving high reliability and low average energy consumption with minor area overhead. To adapt to the variable transient error rates, a configurable error control coding (ECC) scheme is proposed for datalink-layer transient error management. The proposed method can adjust both error detection and error correction capability at runtime by varying the number of redundant wires for parity check bits. The obtained error resilience makes the proposed method suitable for a range of link error rates. Configuring the number of redundant wires to match the noise conditions reduces the average energy consumption in the ECC codec and interconnect link. A hardware efficient implementation for the configurable ECC is presented, as well. We integrate the error control techniques in the datalink and physical layers to co-manage transient and permanent errors. Infrequently used redundant wires for the configurable ECC are utilized as spare wires to replace permanently unusable links. To maintain the transient and permanent error co-management capability as noise conditions change, we propose a packet re-organization algorithm combined with shortening error control coding method. This method reduces the need for energy consuming fault-tolerant routing, minimizing latency and energy overhead induced by error control. This co-management method is suitable for NoCs operating in variable noise conditions with a small number of permanently unusable wires. To further improve energy efficiency, the adaptation on ECC is extended to the network layer. We employ end-to-end error control in the network layer in low noise conditions and enhance the error control capability in high noise conditions by adding hop-to-hop error control in the datalink layer. A protocol that boosts or reduces error control strength is presented to support runtime seamless ECC mode switching. Simply combining end-to-end error control with hop-to-hop error control significantly increases energy consumption. To address this issue, we apply the concept of product codes to the dual-layer error control; the hop-to-hop error control is designed to be compatible with one dimension of the product code. Consequently, the dual-layer cooperative error control can switch error control modes without interrupting normal NoC operation, achieving high reliability and energy efficiency in a wide range of link error rates. To evaluate performance and energy consumption of different error control methods on a large size NoC, we propose a flexible parallel NoC simulator. Plug-and-play error control coding (ECC) insertion and some typical error control codecs have been implemented in the simulator. The flexible fault injection environment provided by our simulator assists error control exploration for specific purposes. In addition, we use C and message passing interface (MPI) languages to schedule parallel simulation on a multiprocessor server, addressing the prohibitive simulation time and system resource challenges caused by the large number of communicating nodes and extensive number of simulation variables"--Leaves iv-vi.
Download or read book Transient and Permanent Error Control for Networks On Chip written by Springer and published by . This book was released on 2012-05-01 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Interconnection Networks written by Jose Duato and published by Morgan Kaufmann. This book was released on 2003 with total page 626 pages. Available in PDF, EPUB and Kindle. Book excerpt: Foreword -- Foreword to the First Printing -- Preface -- Chapter 1 -- Introduction -- Chapter 2 -- Message Switching Layer -- Chapter 3 -- Deadlock, Livelock, and Starvation -- Chapter 4 -- Routing Algorithms -- Chapter 5 -- CollectiveCommunicationSupport -- Chapter 6 -- Fault-Tolerant Routing -- Chapter 7 -- Network Architectures -- Chapter 8 -- Messaging Layer Software -- Chapter 9 -- Performance Evaluation -- Appendix A -- Formal Definitions for Deadlock Avoidance -- Appendix B -- Acronyms -- References -- Index.
Download or read book Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors written by José Rodrigo Azambuja and published by Springer. This book was released on 2016-09-10 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques. The authors then discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time.
