Download or read book Architectures for high throughput and reliable iterative channel decoders written by Matthias May and published by . This book was released on 2013 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book High Throughput VLSI Architectures for Iterative Decoders written by Engling Yeo and published by . This book was released on 2003 with total page 372 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Turbo Decoder Architecture for Beyond 4G Applications written by Cheng-Chi Wong and published by Springer Science & Business Media. This book was released on 2013-10-01 with total page 106 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.

Download or read book High Throughput Low Power Decoder Architectures for Low Density Parity Check Codes written by Anand Manivannan Selvarathinam and published by . This book was released on 2005 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by one third. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cH[superscript]T that computes the number of parity checks in error. Based on cH[superscript]Tvalue, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cH[superscript]T in the first scheme.

Download or read book Digital Satellite Communications written by Giovanni E. Corazza and published by Springer Science & Business Media. This book was released on 2007-12-03 with total page 578 pages. Available in PDF, EPUB and Kindle. Book excerpt: Discusses long-term developments Addresses advanced physical layer techniques designed for broadband communications, for fixed and mobile terminals Considers 4G evolutions and possible convergence between different technologies

Download or read book Guessing Random Additive Noise Decoding written by Syed Mohsin Abbas and published by Springer Nature. This book was released on 2023-08-17 with total page 157 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book gives a detailed overview of a universal Maximum Likelihood (ML) decoding technique, known as Guessing Random Additive Noise Decoding (GRAND), has been introduced for short-length and high-rate linear block codes. The interest in short channel codes and the corresponding ML decoding algorithms has recently been reignited in both industry and academia due to emergence of applications with strict reliability and ultra-low latency requirements . A few of these applications include Machine-to-Machine (M2M) communication, augmented and virtual Reality, Intelligent Transportation Systems (ITS), the Internet of Things (IoTs), and Ultra-Reliable and Low Latency Communications (URLLC), which is an important use case for the 5G-NR standard. GRAND features both soft-input and hard-input variants. Moreover, there are traditional GRAND variants that can be used with any communication channel, and specialized GRAND variants that are developed for a specific communication channel. This book presents a detailed overview of these GRAND variants and their hardware architectures. The book is structured into four parts. Part 1 introduces linear block codes and the GRAND algorithm. Part 2 discusses the hardware architecture for traditional GRAND variants that can be applied to any underlying communication channel. Part 3 describes the hardware architectures for specialized GRAND variants developed for specific communication channels. Lastly, Part 4 provides an overview of recently proposed GRAND variants and their unique applications. This book is ideal for researchers or engineers looking to implement high-throughput and energy-efficient hardware for GRAND, as well as seasoned academics and graduate students interested in the topic of VLSI hardware architectures. Additionally, it can serve as reading material in graduate courses covering modern error correcting codes and Maximum Likelihood decoding for short codes.

Download or read book Architectures for Baseband Signal Processing written by Frank Kienle and published by Springer Science & Business Media. This book was released on 2013-08-15 with total page 268 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book addresses challenges faced by both the algorithm designer and the chip designer, who need to deal with the ongoing increase of algorithmic complexity and required data throughput for today’s mobile applications. The focus is on implementation aspects and implementation constraints of individual components that are needed in transceivers for current standards, such as UMTS, LTE, WiMAX and DVB-S2. The application domain is the so called outer receiver, which comprises the channel coding, interleaving stages, modulator, and multiple antenna transmission. Throughout the book, the focus is on advanced algorithms that are actually in use in modern communications systems. Their basic principles are always derived with a focus on the resulting communications and implementation performance. As a result, this book serves as a valuable reference for two, typically disparate audiences in communication systems and hardware design.

Download or read book Advanced Hardware Design for Error Correcting Codes written by Cyrille Chavet and published by Springer. This book was released on 2014-10-30 with total page 197 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.

Download or read book High Throughput Iterative Decoders written by Engling Yeo and published by Kluwer Academic Publishers. This book was released on 2007-08-01 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt: High Throughput Iterative Decoders: Towards Shannon Bound in VLSI addresses the algorithms and implementations of iterative decoders for error control in communication applications. The iterative codes are based on various concatenated schemes of convolutional codes, also known as turbo codes, and low density parity check (LDPC) codes. The decoding alogirthms are instances of message passing or belief propagation algorithms, which rely on the iterative cooperation between soft-decoding modules known as soft-input-Iterative decoding is a recent advacement in communication theory that is applicable to wireless, wireline, and optical communicatiosn systems. It promises significant advantage in bit-error rate (BER) performance at signal to noise ratios very close to the theoretical capacity bound. However, a direct mapping of the decoding algorithms leads to a multifold increase in the implementation complexity. As deep submicron technology matures, there is a possibility of implementing these applications that were once thought to be too complex to fit onto a single silicon die. We present the architectural and implementation issues related to the VLSI implementation of high throughput iterative decoders. The computational hardware and memory requirements of different competing architectures are discussed. This monograph also introduces reduced complexity modifications of algorithms that provide efficient mapping into architectures and VLSI implementations.

Download or read book Proceedings International Symposium on VLSI Design written by and published by . This book was released on 2005 with total page 938 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Digital Communication Receiver Algorithms and Architectures for Reduced Complexity and High Throughput written by Jun Won Choi and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: In this dissertation, efficient receiver algorithms and architectures for digital communications are studied. As the demand for higher data communication rate increases, the dimension of communication systems is rapidly growing, thereby requiring computationally efficient detection and decoding algorithms in the receiver. Hence, it is crucial to develop receiver algorithms that can offer good performance-complexity trade-offs in high dimensional communication systems such as multi-input multi-output (MIMO) systems and systems with a large delay spread. In this dissertation, computationally efficient receiver algorithms and low-power implementation of receiver architectures are investigated. First, a low-complexity near maximum-likelihood (ML) detector, called the reduced-dimension ML search (RD-MLS), is proposed. The main idea of the RD-MLS is based on reduction of search space dimension. That is, a solution is searched over a subset of symbols to reduce the search complexity. In order to minimize the inevitable performance loss due to the search space reduction, a list tree search (LTS) algorithm is employed, which finds the best K candidates over the reduced search space. A final solution is chosen among the K candidates after extension to the full dimension via an MMSE decision-feedback (MMSE-DF) detector. To determine the candidate size, K adaptively, a stopping criterion is incorporated into the LTS. Through computer simulations, we demonstrate that the RD-MLS algorithm achieves significant complexity reduction over the existing near ML detectors while limiting performance loss to within one dB from ML detection. Second, a low complexity MIMO tree detector, called the improved soft-input soft-output M-algorithm (ISS-MA), is presented. The proposed detector is developed for iterative detection and decoding (IDD) systems, which are known to achieve near-optimal detection performance for MIMO channels. In order to improve the performance of tree detection, a look-ahead path metric is employed that accounts for the impact of unvisited paths of the tree via an unconstrained linear MMSE estimator. Based on an analysis of the probability of correct path loss, we show that the improved path metric offers better detection performance than the conventional path metric. We also demonstrate through simulations that the ISS-MA provides a better performance-complexity trade-off than existing soft-input soft-output detection algorithms. Third, a computationally efficient turbo equalization algorithm for underwater acoustic communications is studied. The performances of two popular linear turbo equalizers, a channel estimate-based minimum mean square error TEQ (CE-based MMSE-TEQ) and a direct-adaptive TEQ (DA-TEQ) technique, are compared in the presence of channel estimation errors and adjustment errors of a least mean square (LMS) adaptive algorithm. Next, an underwater receiver architecture built upon the LMS DA-TEQ technique is introduced. To maintain a performance gains over time-varying channels, the convergence speed of the LMS algorithm is improved via two methods: (1) data reusing and gear-shifting LMS and (2) reducing the length of the equalizer by capturing the sparse structure of underwater acoustic channels. In addition, the sparse structure resulting from the underwater channel can be exploited to reduce the complexity of the equalizer and mitigate error propagation. Receiver performance for different modulation orders, channel codes, and hydrophone configurations was examined at a variety of distances, up to 1 km, from the transmitters. Experimental results show great promise for this approach, as data rates in excess of 15 kbit/s could readily be achieved without error. Lastly, an energy efficient estimation and detection problem is formulated for low-power digital filtering. Building on the soft digital signal processing technique that combines algorithmic noise tolerance and voltage scaling to reduce power, a minimum power soft error cancellation (MP-SEC) technique detects, estimates and corrects transient errors that arise from voltage over-scaling. These timing violation-induced errors, called soft errors, can be detected and corrected by exploiting the correlation structure induced by the filtering operation being protected, together with a reduced-precision replica of the protected operation. By exploiting a spacing property of soft errors in certain architectures, MP-SEC can achieve up to 30 % power savings with no SNR loss and up to 55 % power savings with less than 1 dB SNR loss, according to logic-level simulations performed for an example 25-tap frequency-selective filter.

Download or read book High Performance Embedded Architectures and Compilers written by André Seznec and published by Springer Science & Business Media. This book was released on 2009-01-12 with total page 432 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.

Download or read book Massive MIMO Detection Algorithm and VLSI Architecture written by Leibo Liu and published by Springer. This book was released on 2019-02-20 with total page 348 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

Download or read book Architecture of Computing Systems ARCS 2012 written by Andreas Herkersdorf and published by Springer. This book was released on 2012-02-11 with total page 264 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 25th International Conference on Architecture of Computing Systems, ARCS 2012, held in Munich, Germany, in February/March 2012. The 20 revised full papers presented in 7 technical sessions were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on robustness and fault tolerance, power-aware processing, parallel processing, processor cores, optimization, and communication and memory.

Download or read book Satellite Systems Engineering in an IPv6 Environment written by Daniel Minoli and published by CRC Press. This book was released on 2009-02-03 with total page 360 pages. Available in PDF, EPUB and Kindle. Book excerpt: Capitalize on Expert Foresight into the Future of Satellite Communication Satellite technology will maintain its key role in the evolving communications needs of government, military, IPTV, and mobile video industries because of its intrinsic multicast/broadcast capabilities, mobility aspects, global reach, reliability, and ability to quickly suppo

Download or read book High Performance High Speed VLSI Architectures for Wireless Communication Applications written by Zhipei Chi and published by . This book was released on 2001 with total page 394 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book High Performance Decoder Architectures For Low Density Parity Check Codes written by Kai Zhang and published by . This book was released on 2012 with total page 244 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted to exploring efficient VLSI architectures for high-performance LDPC decoders and LDPC-like detectors in sparse inter-symbol interference (ISI) channels. The performance of an LDPC decoder is mainly evaluated by area efficiency, error-correcting capability, throughput and rate flexibility. With this work we investigate tradeoffs between the four performance aspects and develop several decoder architectures to improve one or several performance aspects while maintaining acceptable values for other aspects ... Layered decoding algorithm, which is popular in LDPC decoding, is also adopted in this paper. Simulation results show that the layered decoding doubles the convergence speed of the iterative belief propagation process. Exploring the special structure of the connections between the check nodes and the variable nodes on the factor graph, we propose an effective detector architecture for generic sparse ISI channels to facilitate the practical application of the proposed detection algorithm. The proposed architecture is also reconfigurable in order to switch flexible connections on the factor graph in the time-varying ISI channels.