Download or read book A Novel Analog Decision feedback Equalizer in Cmos for Serial 10 gb sec Data Transmission Systems written by Soumya Chandramouli and published by . This book was released on 2007 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission over FR-4 backplane and optical fibre. The ADFE overcomes the first feedback-loop latency challenge of traditional digital and mixed-signal DFEs by separating data re-timing from equalization and also eliminates the need for clock-recovery prior to decision-feedback equalization. The ADFE enables 10-Gb/sec decision-feedback equalization using a 0.18-um CMOS process, the first to do so to the author s knowledge. A tuneable current-mode-logic (CML) feedback-loop is designed to enable first post-cursor cancellation for a range of data-rates and to have external control over loop latency over variations in process, voltage and temperature. CML design techniques are used to minimize current consumption and achieve the required voltage swing for decision-feedback to take place. The all-analog equalizer consumes less power and area than comparable state-of-the art DFEs.

Download or read book Dissertation Abstracts International written by and published by . This book was released on 2008 with total page 994 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by Springer. This book was released on 2014-09-22 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).

Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by . This book was released on 2014-10-31 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Circuit Blocks for an Analog CMOS Decision Feedback Equalizer written by Jagdeep Singh Bal and published by . This book was released on 1992 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Partial Analog Equalization and ADC Requirements in Wired Communications microform written by Amir Hadji-Abdolhamid and published by Library and Archives Canada = Bibliothèque et Archives Canada. This book was released on 2004 with total page 312 pages. Available in PDF, EPUB and Kindle. Book excerpt: High-speed high-resolution analog-to-digital converters (ADC) are one of the major bottlenecks in digital communication systems. Every extra bit requirement in a high-speed flash ADC roughly doubles the silicon area and power consumption of the chip and furthermore, complicates ADC design. This thesis investigates the ADC requirements for wired communication applications and presents an efficient partial analog equalization approach to reduce the front-end ADC resolution requirement. In contrast to a full-analog equalizer, a partial analog equalizer (PAE) partially equalizes the channel and is complemented by a digital equalizer. The contributions of this thesis include three major components: (1) An analytical study elaborates and quantifies the benefit of partial equalization in terms of ADC bit requirements. (2) It is shown that a fairly simple PAE circuit can yield most of the available advantage. (3) An implementation of a high-speed PAE/ADC, combined on a single 1.8-V CMOS chip, is demonstrated and the benefit of 2--3 bits improvement is verified, experimentally. Moreover, the optimization of PAE coefficients and the similarity of 2-tap PAE to an analog first-order decorrelator is investigated. The analytical discussions include studying the benefit of PAE in baseband systems with both feedforward and decision feedback equalizers. Similar benefits of PAE in a passband modulation system is also discussed as an appendix for future research direction. The target application for this thesis is 622 Mb/s over a 300-m coaxial cable for serial digital video data transmissions. The proposed PAE along with a 6-bit 400-MHz flash ADC was designed and fabricated in a 0.18-mum CMOS process. The fabricated chip consumes 106 mW of power with 34-dB SNDR at 250 MHz sampling clock. For a 400-Mb/s data transmission over a 240-m coaxial channel, experimental results showed an error performance improvement equivalent to an 8-bit-ADC system.

Download or read book An Adaptive Analog Decision feedback Equalizer written by Michael Q. Le and published by . This book was released on 1998 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Adaptive Decision Feedback Equalization With Continuous time Infinite Impulse Response Filters written by Shayan Shahramian and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: In high-speed (10+Gb/s) chip-to-chip links, the primary impairments to signal integrity are noise, crosstalk, and a smooth tail in the pulse response resulting in inter-symbol interference (ISI) sometimes spanning more than 10 unit intervals (UIs). Although often simple in their implementation, continuous time linear equalizers amplify high-frequency noise and crosstalk and consume extra power. A conventional discrete-time (DT) decision feedback equalizer (DFE) is well-suited and power efficient for channels with a few dominant post-cursor ISI terms, however, the power can become prohibitive for channels with many post-cursor ISI terms. Infinite impulse response (IIR) DFEs can equalize post-cursor ISI persisting 10 or more UIs while consuming low-power comparable to just one DT tap. DFE architectures with varying numbers of DT and IIR taps are compared for use in typical wireline channels, and it is found that 2 IIR taps can offer an excellent compromise between power consumption and performance. However, an IIR DFEâ s performance degrades significantly as the feedback loop delay increases. Fortunately, adding a single DT tap can eliminate the degradation. The first ever hybrid DFE combining 1 DT and multiple (2) IIR taps is presented equalizing 24dB loss at half the bitrate while consuming 4.1mW at 10Gb/s. A novel edge based adaptation algorithm is also presented for DT DFEs which converges faster than previous algorithms while using the same high-speed circuitry and signals required for clock recovery. The edge based algorithm is extended to work for a 1 DT + 1 IIR DFE. The 1 DT + 1 IIR DFE along with integrated clock recovery and adaptation is demonstrated in 28nm FD-SOI CMOS. At 16Gb/s with a 30dB-loss channel, a BER below 10â 12 is measured over a 0.3UI timing window. The novel edge-based algorithm adapts both IIR and discrete-tap equalizer coefficients using the same high-speed circuitry and signals required for clock recovery. The adaptive DFE converges within 5us and is robust in the presence of poorly-conditioned data.

Download or read book Analog and Digital Integrated Circuit Blocks for a Decision Feedback Equalizer written by Shahriar Jamasb and published by . This book was released on 1993 with total page 232 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Reconfigurable Equalization for 10 Gb sec Serial Data Links in a 0 18 m CMOS Technology written by Franklin Young-Jae Bien and published by . This book was released on 2006 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Adaptive Equalization System for Data Transmission Over Coaxial Cables written by Jasmine Sai-Ying Cheng and published by . This book was released on 1998 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: An adaptive equalization system for data transmission over coaxial cables is proposed. It is intended to combat intersymbol interference for 4-level baseband PAM encoded data at 311Mbits/second transmitted over a coaxial cable, the length of which can be varied from 0 to 300 meters. The equalization system is composed of an adaptive analog equalizer followed by an adaptive decision feedback equalizer in order to improve the signal-to-noise ratio. The adaptive analog equalizer contains a unity-gain feedforward path and a bandpass filter, and uses one tuning parameter to provide equalization for different cable lengths. A second-order analog filter which is used to implement the adaptive analog equalizer in a 0.5$\mu$m CMOS process is presented in full detail.

Download or read book Electrical Electronics Abstracts written by and published by . This book was released on 1997 with total page 1904 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Design Techniques for High speed Low power Flash A D Converters in 0 13 mu m CMOS Technology written by Darya Mohtashemi and published by . This book was released on 2013 with total page 91 pages. Available in PDF, EPUB and Kindle. Book excerpt: In high-speed data communication systems, some form of channel equalization is necessary to provide error-free data transmission. Analog techniques, such as feed-forward equalizers (FFEs) and decision feedback equalizers (DFEs) are often used, and analog FFEs and DFEs working at bit rates up to 40 Gb/s exist; however, since digital equalization is more robust and offers a higher level of flexibility, it is becoming the preferred choice over analog equalization. Therefore, high-speed analog-to-digital converters (ADCs) are becoming fundamental components of high-speed communication systems. The bottleneck in such systems is the design of the ADC with reasonable power dissipation. This thesis focuses on the challenges of high-speed, low power, low bit-error-rate ADC design. An 8 GS/s, non-interleaved, 4 bit flash ADC is proposed and the high-speed design techniques used in the development of this A/D converter are presented. A novel comparator circuit, which demonstrates higher bandwidth compared to existing architectures - without the use of bandwidth enhancing inductors - is proposed. Also, a novel metastability detection circuit, which results in power-efficient metastability error reduction, is introduced. A commonly used technique to reduce the metastability error probability in high-speed flash ADCs, is to pipeline latches at the comparator outputs. This results in an increase in the power dissipation and area of the converter. By incorporating this detection circuit in the ADC, low BER can be achieved with minimal power and area overhead.

Download or read book Equalizers for Digital Modems written by A. P. Clark and published by John Wiley & Sons. This book was released on 1985 with total page 488 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Circuit Techniques for Implementation of High Speed CMOS Analog Adaptive Decision Feedback Equalizers written by Bin Qi and published by . This book was released on 1996 with total page 138 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Design of High speed Low power Analog CMOS Decision Feedback Equalizers written by Wenjun Su and published by . This book was released on 1996 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt: Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using digital FIR filters preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the major contributers to the power dissipation. However, this project focuses on the analog IC implementations of the DFE to achieve high speed and low power consumption. In other words, this project gets intensively involved in the design of a large-input highly-linear voltage-to-current converter, the design of a high-speed low-power 6-bit comparator, and the design of a high-speed low-power 6-bit current-steering D/A converter. The design and layout for the proposed analog equalizer are carried out in a 1.2 pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz clock frequency and 6-bit accuracy can be easily achieved. The power consumption for all the analog circuits is only about 24mW operating under a single 5V power supply.

Download or read book A Mixed signal Decision feedback Equalizer Using a Look ahead Architecture written by Ravinder Singh Kajley and published by . This book was released on 1996 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt: