Download or read book Wafer Scale Integration written by Earl E. Swartzlander Jr. and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 515 pages. Available in PDF, EPUB and Kindle. Book excerpt: Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.
Download or read book Wafer Scale Integration III written by Mariagiovanna Sami and published by North Holland. This book was released on 1990 with total page 420 pages. Available in PDF, EPUB and Kindle. Book excerpt: The purpose of this book is to give an up-to-date presentation of architectures and technologies for wafer-scale integration. As such, it is an overview of the work of the leading research centers active in this area, and an outline of expected evolution and progress in the subject. New technological solutions are envisioned; while the use of optical technologies for interconnections promises to overcome one of the main restrictions to architectures on a wafer, the extension of quick-prototyping solutions to the wafer dimension allows the introduction of wafer-scale systems in educational environments as well as in applications where a quick result and limited production would make traditional silicon solutions unacceptable. Regarding architectures and their applications, three different lines of approach can be identified. Evolutive solutions are proposed, mainly concerning array architectures and restructuring techniques. Innovative architectures are presented, several papers dealing with neural nets. There are also architectures designed not just for experimental reasons but for industrial production. Overall, non-numerical applications predominate.
Download or read book Wafer scale integration 3 written by and published by . This book was released on 1989 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wafer scale integration 1 written by and published by . This book was released on 1986 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wafer Level Integrated Systems written by Stuart K. Tewksbury and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 456 pages. Available in PDF, EPUB and Kindle. Book excerpt: From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.
Download or read book International Conference on Wafer Scale Integration Proceedings San Francisco California USA written by and published by . This book was released on 1992 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Soft Configurable Wafer Scale Integration written by M. G. Blatt and published by . This book was released on 1990 with total page 258 pages. Available in PDF, EPUB and Kindle. Book excerpt: The redundancy models constrain wafer yield by system requirements such as the minimum number of working circuit units, and whether these working units are distributed evenly around the wafer. Choice of redundancy model significantly affects the resulting wafer yield."
Download or read book Wafer scale integration 2 written by and published by . This book was released on 1987 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wafer Scale Integration written by Michael J. Little and published by . This book was released on 1990 with total page 342 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Models for Wafer Scale Integration Implementation written by Timothy Lyman Michalka and published by . This book was released on 1988 with total page 472 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Post Processor for Wafer Scale Integration written by Michael C. Stanton and published by . This book was released on 1987 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Standard Test Interface for Wafer Scale Integration written by Padmaraj Singh and published by . This book was released on 1991 with total page 162 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book 1991 Proceedings written by Michael J. Little and published by . This book was released on 1991 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wafer Scale Integration International Conference On written by and published by . This book was released on with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wafer Scale Integration of Configurable Highly Parallel Processors written by Kye Sherrick Hedlund and published by . This book was released on 19?? with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Wafer Level 3 D ICs Process Technology written by Chuan Seng Tan and published by Springer Science & Business Media. This book was released on 2009-06-29 with total page 365 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
Download or read book Wafer Scale Integration written by Joe E. Brewer and published by . This book was released on 1993 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt:
