Download or read book Tutorial Test Generation for VLSI Circuits written by Sharad C. Seth and published by . This book was released on 1987 with total page 102 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Tutorial Test Generation for VLSI Chips written by Vishwani D. Agrawal and published by IEEE Computer Society Press. This book was released on 1988 with total page 426 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Tutorial VLSI Testing Validation Techniques written by Hassan K. Reghbati and published by . This book was released on 1985 with total page 630 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits written by M. Bushnell and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 690 pages. Available in PDF, EPUB and Kindle. Book excerpt: The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Download or read book Test Generation of Crosstalk Delay Faults in VLSI Circuits written by S. Jayanthy and published by Springer. This book was released on 2018-09-20 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.
Download or read book A High Level Approach to Test Generation for VLSI Circuits written by Prakash Narain and published by . This book was released on 1992 with total page 128 pages. Available in PDF, EPUB and Kindle. Book excerpt: The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator. The data path is modeled using a data flow graph. The gate level test generation concepts of propagation, justification and implication have been extended to high level. A dependency directed backtracking scheme has been designed for the algorithm. The control circuit for test generation is modeled as a gate level interconnection of primitives. The data path is modeled as a high level interconnection. A sequential circuit test generation algorithm has been designed based upon forward time processing. A novel concept of initialization inference has been introduced. Both of the approaches have been demonstrated to be very effective.
Download or read book Power Constrained Testing of VLSI Circuits written by Nicola Nicolici and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt: This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
Download or read book Logic Verification and Test Generation for VLSI Circuits written by Ruey-sing Wei and published by . This book was released on 1986 with total page 548 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Development of an Automatic Test Pattern Generation System for VLSI Circuits written by Kuljit S. Bains and published by . This book was released on 1990 with total page 310 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Automatic Test Generation for Electron beam Testing of VLSI Circuits written by Richard John Kinch and published by . This book was released on 1982 with total page 294 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits written by Ilker Hamzaoglu and published by . This book was released on 1999 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Hierarchical Modeling for VLSI Circuit Testing written by Debashis Bhattacharya and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Download or read book Test Generation by Fault Sampling written by Hassan A. Farhat and published by . This book was released on 1988 with total page 268 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book VLSI Test Generation written by Sharad C. Seth and published by . This book was released on 1988 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book The Implementation of a Complete Test Generation System for LSI VLSI Circuits written by Albers H. Wang and published by . This book was released on 1987 with total page 190 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Techniques to Speedup Test Generation for VLSI Circuits written by University of Illinois at Urbana-Champaign. Coordinated Science Laboratory. Computer Systems Group and published by . This book was released on 1989 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt: The increasing complexity of logic circuits has made the problem of test generation intractable. In this dissertation we investigate three different techniques to speed up the test generation process. The first approach attempts to exploit the hierarchy inherent in any complex digital design. An intermediate high-level representation is proposed, and algorithms to perform forward implication and backtracing in the proposed framework are developed. Results of test generation experiments based on this approach are also presented. The second technique deals with the use of heuristics in test generation algorithms. Based on an extensive study of five existing testability measures, a composite test generation strategy is evaluated. The composite strategy uses multiple testability measures to aid the test generation guidance heuristic. Our results indicate that this strategy not only gives better fault coverage but also reduces the average time taken per fault. Finally we investigate the viability of parallel processing for test generation. Schemes for mapping test generation algorithms onto different classes of parallel machines are presented. The performance of these mapping strategies is predicted based on uniprocessor turnaround times and an estimate of the communication delays.
