Download or read book Timing Skew Calibration for Time Interleaved Analog to Digital Converters written by Luke Wang and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Background Calibration of Time Interleaved Data Converters written by Manar El-Chammas and published by Springer Science & Business Media. This book was released on 2011-12-17 with total page 138 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes techniques for time-interleaving a number of analog-to-digital data converters to achieve demanding bandwidth requirements. Readers will benefit from the presentation of a low-power solution that can be used in actual products, while alleviating the time-varying signal artifacts that typically arise when implementing such a system architecture.

Download or read book Background Calibration of Timing Skew in Time interleaved A D Converters written by Manar Ibrahim El-Chammas and published by Stanford University. This book was released on 2010 with total page 155 pages. Available in PDF, EPUB and Kindle. Book excerpt: The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This thesis introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC's comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.

Download or read book 2021 18th International SoC Design Conference ISOCC written by IEEE Staff and published by . This book was released on 2021-10-06 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: SoC, Analog Circuits, Digital Circuits, Data Converters, RF Microwave Wireless Circuits, Memories, Design Methodology, Circuits and Systems for Emerging Technologies, AI

Download or read book Digital Background Calibration of Time interleaved Analog to digital Converters written by Shafiq M. Jamal and published by . This book was released on 2001 with total page 262 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Calibration of Sampling Clock Skew in High speed High resolution Time interleaved ADCs written by Daniel Prashanth Kumar and published by . This book was released on 2015 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt: There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.

Download or read book Digital Calibration of Double sampled Time interleaved Analog to digital Converters written by Chi Ho Law and published by . This book was released on 2009 with total page 290 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Blind Calibration for Time interleaved Analog to digital Converters written by Yuhui Huang and published by . This book was released on 2006 with total page 326 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Time interleaved Analog to Digital Converters written by Simon Louwsma and published by Springer Science & Business Media. This book was released on 2010-09-08 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.

Download or read book Signal Reconstruction Algorithms for Time Interleaved ADCs written by Anu Kalidas Muralidharan Pillai and published by Linköping University Electronic Press. This book was released on 2015-05-22 with total page 100 pages. Available in PDF, EPUB and Kindle. Book excerpt: An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TIADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs. Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor. Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lower rate. However, the reduced sampling rate comes at the cost of additional digital signal processing that is needed to reconstruct the uniform-grid sequence from the sub-Nyquist sampled sequence obtained via CNUS. The existing reconstruction scheme is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. Also, in applications where the band locations of the sparse multi-band signal can change from time to time, the reconstructor should support online reconfigurability. Here, we propose a reconstruction scheme that reduces the computational complexity of the reconstructor and at the same time, simplifies the online reconfigurability of the reconstructor. Finally, we consider a class of nonuniformly sampled signals which occur at the output of TI-ADCs that use some of the input sampling instants for sampling a known calibration signal. The samples corresponding to the calibration signal are used for estimating the channel mismatch parameters. In such TI-ADCs, nonuniform sampling is due to the mismatches between the channel ADCs and due to the missing input samples corresponding to the sampling instants reserved for the calibration signal. We propose three reconstruction schemes for such nonuniformly sampled signals and show using design examples that, compared to a previous solution, the proposed schemes require substantially lower computational complexity.

Download or read book Mismatch Calibration of Time interleaved Digital to analog Converters written by Rowena J. D'souza and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book CMOS Data Converters for Communications written by Mikael Gustavsson and published by Springer Science & Business Media. This book was released on 2006-04-18 with total page 378 pages. Available in PDF, EPUB and Kindle. Book excerpt: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

Download or read book Time interleaved Analog to digital Converters for Digital Communications written by Tsung-Heng Tsai and published by . This book was released on 2005 with total page 206 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Advanced Data Converters written by Gabriele Manganaro and published by Cambridge University Press. This book was released on 2011-11-17 with total page 251 pages. Available in PDF, EPUB and Kindle. Book excerpt: Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.

Download or read book Nyquist AD Converters Sensor Interfaces and Robustness written by Arthur H.M. van Roermund and published by Springer Science & Business Media. This book was released on 2012-11-26 with total page 291 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is based on the 18 presentations during the 21st workshop on Advances in Analog Circuit Design. Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

Download or read book Generalized Low Voltage Circuit Techniques for Very High Speed Time Interleaved Analog to Digital Converters written by Sai-Weng Sin and published by Springer Science & Business Media. This book was released on 2010-09-29 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.

Download or read book Multi Gigahertz Nyquist Analog to Digital Converters written by Athanasios T. Ramkaj and published by Springer Nature. This book was released on 2023-01-12 with total page 289 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book proposes innovative circuit, architecture, and system solutions in deep-scaled CMOS and FinFET technologies, which address the challenges in maximizing the accuracy*speed/power of multi-GHz sample rate and bandwidth Analog-to-Digital Converters (ADC)s. A new holistic approach is introduced that first identifies the major error sources of a converter’ building blocks, and quantitatively analyzes their impact on the overall performance, establishing the fundamental circuit-imposed accuracy – speed – power limits. The analysis extends to the architecture level, by introducing a mathematical framework to estimate and compare the accuracy – speed – power limits of several ADC architectures and variants. To gain system-level insight, time-interleaving is covered in detail, and a framework is also introduced to compare key metrics of interleaver architectures quantitatively. The impact of technology is also considered by adding process effects from several deep-scaled CMOS technologies. The validity of the introduced analytical approach and the feasibility of the proposed concepts are demonstrated by four silicon prototype Integrated Circuits (IC)s, realized in ultra-deep-scaled CMOS and FinFET technologies. Introduces a new, holistic approach for the analysis and design of high-performance ADCs in deep-scaled CMOS technologies, from theoretical concepts to silicon bring-up and verification; Describes novel methods and techniques to push the accuracy – speed – power boundaries of multi-GHz ADCs, analyzing core and peripheral circuits’ trade-offs across the entire ADC chain; Supports the introduced analysis and design concepts by four state-of-the-art silicon prototype ICs, implemented in 28nm bulk CMOS and 16nm FinFET technologies; Provides a useful reference and a valuable tool for beginners as well as experienced ADC design engineers.