Download or read book Test Generation for Detecting Multiple Stuck Faults in Synchronous Sequential Circuits Using Boolean Difference and Transition Matrix Techniques written by Thiep V. Nguyen and published by . This book was released on 1993 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is a mathematical concept which has proved its usefulness in the study of single and multiple stuck-at faults in combinational circuits. This tool of analysis was extended to cover multiple stuck-at faults in synchronous sequential circuits as well. In this dissertation, modifications to previous work are presented, together with the development of a new method for deriving the required shortest test sequence to detect a specified multiple fault. First, the vector Boolean difference technique is utilized to determine the input vector that will produce a difference in output between the fault-free and faulty circuits with both starting in the same initial state. If that detection cannot be achieved immediately, then the state transition matrices of both circuits are combined and used to form a matrix of detecting state pairs. Each of these pairs comprises of the present states of both circuits for which an output difference will be detected by an input vector. The detecting tree is then built leading the two circuits from the same initial state to the first detecting state found to complete the search for the shortest test sequence. Besides being able to identify, at an early stage, faults that are undetectable, this algorithm guarantees the generation of a shortest test sequence, if one exists, for every multiple stuck-at fault in a synchronous sequential circuit having a synchronizing sequence or a known initial state. A computer program was also written as a tool to automatically generate test sequences for detecting single or multiple faults in both combinational and synchronous sequential circuits.
Download or read book Test Generation for Detecting Multiple Stock Faults in Synchronous Sequential Circuits Using Boolean Difference and Transition Matrix Techniques written by Thiep V. Nguyen and published by . This book was released on 1993 with total page 170 pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is a mathematical concept which has proved its usefulness in the study of single and multiple stuck-at faults in combinational circuits. This tool of analysis was extended to cover multiple stuck-at faults in synchronous sequential circuits as well. In this dissertation, modifications to previous work are presented, together with the development of a new method for deriving the required shortest test sequence to detect a specified multiple fault. First, the vector Boolean difference technique is utilized to determine the input vector that will produce a difference in output between the fault-free and faulty circuits with both starting in the same initial state. If that detection cannot be achieved immediately, then the state transition matrices of both circuits are combined and used to form a matrix of detecting state pairs. Each of these pairs comprises of the present states of both circuits for which an output difference will be detected by an input vector. The detecting tree is then built leading the two circuits from the same initial state to the first detecting state found to complete the search for the shortest test sequence. Besides being able to identify, at an early stage, faults that are undetectable, this algorithm guarantees the generation of a shortest test sequence, if one exists, for every multiple stuck-at fault in a synchronous sequential circuit having a synchronizing sequence or a known initial state. A computer program was also written as a tool to automatically generate test sequences for detecting single or multiple faults in both combinational and synchronous sequential circuits.
Download or read book Delay Test Generation for Synchronous Sequential Circuits written by S. Devadas and published by . This book was released on 1989 with total page 11 pages. Available in PDF, EPUB and Kindle. Book excerpt: We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented. (RRH).
Download or read book Combinational Test Generation for Sequential Circuits written by Yong Chang Kim and published by . This book was released on 2002 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Analysis of Multiple Faults in Synchronous Sequential Circuits by Boolean Difference Techniques written by and published by . This book was released on 1978 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is a mathematical concept which has found significant application in the study of single and multiple ''stuck at'' faults in combinational logic circuits. The concept of vector Boolean difference is extended to the analysis of multiple stuck-at faults in synchronous sequential circuits. A vector Boolean difference technique is utilized to determine the set of input/state pairs that will produce a difference in either output or next-state between the fault-free and faulty circuits. Assuming that the fault-free and faulty circuits start in the same initial state, they must be driven by applying a sequence of input vectors to a state in which either a difference in output or next-state is evidenced. If a difference in output cannot be achieved immediately, a second sequence of input vectors must be applied in order to propagate the state difference to the output. Methods for combining the Boolean difference analysis with techniques for deriving the required input vector sequence are discussed.
Download or read book A Study of Fault Diagnosis of Sequential Logic Networks written by B. D. Carroll and published by . This book was released on 1974 with total page 25 pages. Available in PDF, EPUB and Kindle. Book excerpt: The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Download or read book On the Generation of Test Patterns for Multiple Faults written by Younès Karkouri and published by . This book was released on 1992 with total page 35 pages. Available in PDF, EPUB and Kindle. Book excerpt: The method uses similar techniques to those in the FAN and SOCRATES algorithms to guide the search part of the algorithm and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults."
Download or read book Rational Fault Analysis written by Richard Saeks and published by Marcel Dekker. This book was released on 1977 with total page 264 pages. Available in PDF, EPUB and Kindle. Book excerpt: Information on the development of rational procedures for detection, location, & prediction of faults in a variety of systems. Includes a chapter on computer-aided fault analysis.
Download or read book Fault Detection Through Parallel Processing in Boolean Algebra written by Donnamaie E. White and published by . This book was released on 1975 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt: This presentation is an overview of the research in progress on fault detection methods for circuits, both combinational circuits and sequential circuits. A summary of some of the existing techniques for minimal test set generation is followed by an introduction to the concept and theory of a minimal test sequence as a new approach for fault detection in combinational circuits. A detailed explanation of Triadic Graph Theory is followed by a summary of the existing techniques for parallel processing in Boolean Algebra. The main contribution of this paper is the extension of the applications of the Boolean Analyzer to the generation of: (1) Boolean Differences; (2) 'stuck-at' fault tests for a circuit (similar to those generated by Roth's D-Algorithm); and (3) the Test Sequence(s) of a circuit.
Download or read book Symbolic Functional Test Generation with Guaranteed Low level Fault Detection written by Mark Charles Hansen and published by . This book was released on 1996 with total page 330 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multiple Fault Analysis in Synchronous Sequential Circuits by Means of Vector Boolean Difference written by and published by . This book was released on 1977 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The Boolean difference is an elegant mathematical concept which has found significant application in the study of single faults of a stuck-at nature in combinational logic circuits. Recently, several authors have extended this technique to the analysis of multiple faults in combinational circuits. The concept of vector Boolean difference is further extended to the analysis of multiple stuck-at faults in synchronous sequential circuits.
Download or read book Fault Diagnosis of Digital Circuits written by V. N. Yarmolik and published by John Wiley & Sons. This book was released on 1990 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: The continual explosion of computer development has led to inadequate coverage of proper & useful on-line testing techniques. This text fills the gap in the literature by presenting the latest techniques available for digital devices used in the most popular computers. Initial chapters explore the classic problems of on-line testing, pointing out the limited applications of conventional approaches to the problem of diagnosing digital devices using LSI & VLSI chips. Chapters 4-7 cover compact testing methods used to diagnose complex digital circuits. Chapters 8 & 9 analyze the techniques of compressing output responses of a digital circuit, while chapter 10 surveys promising recent signature generation techniques for binary sequences. The final chapter covers multi-output digital circuits.
Download or read book Spectral Techniques and Fault Detection written by Mark G. Karpovsky and published by . This book was released on 1985 with total page 632 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Assessing Fault Model and Test Quality written by Kenneth M. Butler and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt: For many years, the dominant fault model in automatic test pattern gen eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.
Download or read book Test Pattern Generation for Realistic Bridge Faults in CMOS ICs written by F. Joel Ferguson and published by . This book was released on 1991 with total page 28 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Two approaches have been used to balance the cost of generating effective tests for ICs and the need to increase the IC's quality level. The first approach favors using high-level fault models to reduce test generation costs at the expense of test quality, and the second approach favors the use of low-level, technology-specific fault models to increase defect coverage but lead to unacceptably high test generation costs. In this report we (1) present the results of simulations of complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck-at test sets; (2) show how low-level bridge fault models can be incorporated into high-level test generation; and (3) describe our system for generating effective tests for bridge faults and report on its performance."
Download or read book Boolean Approaches in Digital Diagnosis written by and published by . This book was released on 1989 with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt: The goal of this thesis is to review and improve two existing methods that use Boolean reasoning as a basis for testing digital circuits. Extensions are made to research done by both Cerny and Kainec in this area. The method developed by Cerny to generate test vectors capable of detecting single stuck- at, bridge and multiple stuck-at faults is reviewed and then extended in two ways. The first extension incorporates the capability to automatically analyze the results gained from applying a given vector. The second extension allows the diagnosis of sequential circuits. Since Cerny's original method was not automated the entire process is updated to include the extensions and then programmed. Kainec developed an automated diagnostic system to test for multiple faults in combinational circuits. The original system is restricted to diagnosing faults in circuits with one output. An extension is designed and programmed to incorporate the capability to diagnose multiple output circuits. The extension shows that multiple output circuits offer the added advantage of being able to choose an optimal test vector from a set of generated vectors, thereby shortening the required testing time for a given circuit. The software routines are programmed in PC-Scheme (a dialect of LISP) on an IBM microcomputer. Due to a conversion program written by Kainec the software can also be run on a Sun-4 workstation in the T environment. T is derived from Scheme. (jhd).
Download or read book High Level Test Methodology for Crosstalk Faults in Sequential Circuits written by Marong Phadoongsidhi and published by . This book was released on 2004 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt:
