Download or read book Power minimisation techniques for testing low power VLSI circuits written by Nicola Nicolici and published by . This book was released on 2000 with total page 268 pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. The first part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits. Since the proposed test application strategy depends only on controlling primary input change time, power is minimised with no penalty in test area, performance, test efficiency, test application time or volume of test data. Furthermore, it is shown that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. To achieve power savings in large scan sequential circuits a new test set independent multiple scan chain-based technique which employs a new design for test (DFT) architecture and a novel test application strategy, is presented. The technique has been validated using benchmark examples, and it has been shown that power is minimised with low computational time, low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power minimisation techniques for testing low power VLSI circuits using built-in self-test (BIST) at RTL. First, it is important to overcome the shortcomings associated with traditional BIST methodologies. It is shown how a new BIST methodology for RTL data paths using a novel concept called test compatibility classes (TCC) overcomes high test application time, BIST area overhead, performance degradation, volume of test data, fault-escape probability, and complexity of the testable design space exploration. Second, power minimisation in BIST RTL data paths is achieved by analysing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms. Third, the new BIST methodology has been validated using benchmark examples. Further, it is shown that when the proposed power conscious test synthesis and test scheduling is combined with novel test compatibility classes simultaneous reduction in test application time and power dissipation is achieved with low overhead in computational time.
Download or read book Power Constrained Testing of VLSI Circuits written by Nicola Nicolici and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt: This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
Download or read book Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits written by and published by . This book was released on with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to addresses these challenges during test. The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The proposed BS-LFSR is then extended for use in test-per-scan BIST. The results obtained while scanning in test vectors show up to 60% reduction in average power consumption. The BS-LFSR is then extended further to act as a multi-degree smoother for test patterns generated by conventional LFSRs before applying them to the CUT. Experimental results show up to 55% reduction in average power. Another technique that aims to reduce peak power in scan-based BIST is presented. The new technique uses a two-phase scan-chain ordering algorithm to reduce average and peak power in scan and capture cycles. Experimental results show up to 65% and 55% reduction in average and peak power, respectively. Finally, a technique that aims to significantly increase the fault coverage in test-per-scan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques.
Download or read book Practical Low Power Digital VLSI Design written by Gary K. Yeap and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 222 pages. Available in PDF, EPUB and Kindle. Book excerpt: Practical Low Power Digital VLSI Design emphasizes the optimization and trade-off techniques that involve power dissipation, in the hope that the readers are better prepared the next time they are presented with a low power design problem. The book highlights the basic principles, methodologies and techniques that are common to most CMOS digital designs. The advantages and disadvantages of a particular low power technique are discussed. Besides the classical area-performance trade-off, the impact to design cycle time, complexity, risk, testability and reusability are discussed. The wide impacts to all aspects of design are what make low power problems challenging and interesting. Heavy emphasis is given to top-down structured design style, with occasional coverage in the semicustom design methodology. The examples and design techniques cited have been known to be applied to production scale designs or laboratory settings. The goal of Practical Low Power Digital VLSI Design is to permit the readers to practice the low power techniques using current generation design style and process technology. Practical Low Power Digital VLSI Design considers a wide range of design abstraction levels spanning circuit, logic, architecture and system. Substantial basic knowledge is provided for qualitative and quantitative analysis at the different design abstraction levels. Low power techniques are presented at the circuit, logic, architecture and system levels. Special techniques that are specific to some key areas of digital chip design are discussed as well as some of the low power techniques that are just appearing on the horizon. Practical Low Power Digital VLSI Design will be of benefit to VLSI design engineers and students who have a fundamental knowledge of CMOS digital design.
Download or read book Low Power Digital VLSI Design written by Abdellatif Bellaouar and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 539 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-Power Digital VLSI Design: Circuits and Systems addresses both process technologies and device modeling. Power dissipation in CMOS circuits, several practical circuit examples, and low-power techniques are discussed. Low-voltage issues for digital CMOS and BiCMOS circuits are emphasized. The book also provides an extensive study of advanced CMOS subsystem design. A low-power design methodology is presented with various power minimization techniques at the circuit, logic, architecture and algorithm levels. Features: Low-voltage CMOS device modeling, technology files, design rules Switching activity concept, low-power guidelines to engineering practice Pass-transistor logic families Power dissipation of I/O circuits Multi- and low-VT CMOS logic, static power reduction circuit techniques State of the art design of low-voltage BiCMOS and CMOS circuits Low-power techniques in CMOS SRAMS and DRAMS Low-power on-chip voltage down converter design Numerous advanced CMOS subsystems (e.g. adders, multipliers, data path, memories, regular structures, phase-locked loops) with several design options trading power, delay and area Low-power design methodology, power estimation techniques Power reduction techniques at the logic, architecture and algorithm levels More than 190 circuits explained at the transistor level.
Download or read book Low Power VLSI Design and Technology written by Gary K. Yeap and published by World Scientific. This book was released on 1996 with total page 136 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-power and low-energy VLSI has become an important issue in today's consumer electronics.This book is a collection of pioneering applied research papers in low power VLSI design and technology.A comprehensive introductory chapter presents the current status of the industry and academic research in the area of low power VLSI design and technology.Other topics cover logic synthesis, floorplanning, circuit design and analysis, from the perspective of low power requirements.The readers will have a sampling of some key problems in this area as the low power solutions span the entire spectrum of the design process. The book also provides excellent references on up-to-date research and development issues with practical solution techniques.
Download or read book Power Aware Testing and Test Strategies for Low Power Devices written by Patrick Girard and published by Springer Science & Business Media. This book was released on 2010-03-11 with total page 376 pages. Available in PDF, EPUB and Kindle. Book excerpt: Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.
Download or read book Minimizing and Exploiting Leakage in VLSI Design written by Nikhil Jayakumar and published by Springer Science & Business Media. This book was released on 2009-12-02 with total page 229 pages. Available in PDF, EPUB and Kindle. Book excerpt: Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.
Download or read book VLSI Architecture written by Brian Randell and published by Prentice Hall International (UK). This book was released on 1983 with total page 456 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Low Power VLSI Design written by Angsuman Sarkar and published by Walter de Gruyter GmbH & Co KG. This book was released on 2016-08-08 with total page 324 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book teaches basic and advanced concepts, new methodologies and recent developments in VLSI technology with a focus on low power design. It provides insight on how to use Tanner Spice, Cadence tools, Xilinx tools, VHDL programming and Synopsis to design simple and complex circuits using latest state-of-the art technologies. Emphasis is placed on fundamental transistor circuit-level design concepts.
Download or read book Low Power High Fault Coverage Test Techniques for Digital Vlsi Circuits written by Abdallatif S. Abuissa and published by . This book was released on 2009 with total page 129 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Strategies to Reduce Power During VLSI Circuit Testing written by Subhadip Kundu and published by . This book was released on 2012-09-25 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Low Power VLSI Circuits and Systems written by Ajit Pal and published by . This book was released on 2014-12-31 with total page 428 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Logic Synthesis for Low Power VLSI Designs written by Sasan Iman and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 239 pages. Available in PDF, EPUB and Kindle. Book excerpt: Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
Download or read book Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages written by Phani Kameswara Abhishikth Varanasi and published by . This book was released on 2015 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt: The advancements and scaling in technology are continuously increasing in accordance with Moore's Law. This results in an increase in the performance of chips, but comes with a price due to the increased power consumption, and hence resources are spent on cooling, packaging and other methods to reduce the after effects. This additional cost has to be eliminated, and the most obvious solution is to reduce the power consumption of a design which would also protect the chips from permanent failure due to additional heat in the chips. Various power reduction methods including supply voltage scaling, dynamic voltage and frequency scaling, multi voltage design, clock gating for dynamic power reduction, and multi-Vth technique, power gating for leakage power reduction have been proposed. The main aim of our research was to reduce the supply voltage which has a quadruple effecton reducing the power consumption, and hence operate the designs in or as close to the subthreshold region of operation as possible. This kind of ultra low power designs are especially useful in biomedical applications. Carry skip adder and magnitude comparator designs are considered for our research due to the extensive use of such designs in almost all arithmetic applications. Simulations are performed at 45nm CMOS technology and at very low voltages, (e.g., 0.4V) to check the functionality first, followed by the application of some of the most widely used power reduction techniques in the industry, including clock gating and power gating, to test their effectiveness at such low voltages. Error detection sequential circuits were also employed to check if they can further reduce the power consumption and improve the performance of the designs with ultra low supply voltages. The results obtained give interesting insights into the effectiveness of various power reduction techniques at ultra low voltages.
Download or read book Low Power Cmos Vlsi Circuit Design written by Kaushik Roy and published by John Wiley & Sons. This book was released on 2009-02-02 with total page 380 pages. Available in PDF, EPUB and Kindle. Book excerpt: This is the first book devoted to low power circuit design, and its authors have been among the first to publish papers in this area.· Low-Power CMOS VLSI Design· Physics of Power Dissipation in CMOS FET Devices· Power Estimation· Synthesis for Low Power· Design and Test of Low-Voltage CMOS Circuits· Low-Power Static Ram Architectures· Low-Energy Computing Using Energy Recovery Techniques· Software Design for Low Power
Download or read book Low Power VLSI Circuits and Systems written by Ajit Pal and published by Springer. This book was released on 2014-11-17 with total page 417 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.
