Download or read book Modified Pattern Generator of Built in Self Test for Sequential Circuits with Reduced Test Time written by Muhamad Ridzuan Radin Muhamad Amin and published by . This book was released on 2011 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Automatic Test Pattern Generator for Full Scan Sequential Circuits Using Limited Scan Operations written by Vinod Pagalone and published by . This book was released on 2006 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt: In testing sequential circuits with scan chains, the test application time is the main factor that determines the overall cost of testing the circuit. For these circuits, the test application time principally depends on the number flip-flops as well as the number of vectors in the test set. Though test set compaction is one way of reducing test application time, for a significant reduction in testing costs the duration of scan operation has to be reduced. The proposed method achieves this by using limited scan operations where the number of shifts is smaller that the actual length of the scan chain. Thus the compacted test set consists of limited scan operations in places where the scan operation cannot be dropped completely. The method uses an iterative procedure that identifies the vectors that have high fault coverage with minimal shifts in the scan chain.
Download or read book Deterministic Automatic Test Pattern Generation for Built in Self Test System written by Muhammad Nazir Mohammed Khalid and published by . This book was released on 2006 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly designed with Built-In Self Test facility. For this reason, development of test pattern for BIST based on combination of Linear Feedback Shift Register (LFSR) and deterministic ATPG (DATPG) approach could provide more solutions, such as reduce testing time, high fault coverage and low area overhead. One of the key challenges in BIST is the design of the Test Pattern Generation (TPG) that promised high fault coverage. The test pattern generation can be generated either manually or automatically. Problems related to ATPG are linked to the controllability and observability of the nodes in circuits. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational circuit. To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. Altera Max+plus II software is used to simulate the DATPG design to achieve the minimum test patterns for digital combinational circuit. The simulation result will be presented in the form of waveform. The results of DATPG for digital combinational circuit show that the sequence of LFSR has been reduced significantly. In BIST application, the minimum test patterns are applied to the adder/substractor (A/S) known as circuit under test (CUT). A parallel A/S is chosen as a CUT due to the simplicity of the circuit architecture. The A/S is used to verify the proposed DATPG performance. Only one basic cell of the parallel A/S is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both A/S inputs simultaneously. By reducing the number of test pattern, the testing time to market and manufacturing time is expected to reduce leading to reduction in the product cost.
Download or read book Modified Geffe Test Pattern Generator for Built in Self test written by and published by . This book was released on 2002 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Unlike linear Finite State Machines (FSM) such as Linear Feedback Shift Registers (LFSR), the Geffe generator, a nonlinear FSM, hasn't been frequently studied or used in the scenario of digital system testing. Such machines are used as pattern generators for built-in self-test. LFSRs have become widely used in today's integrated circuits since they have a comparatively low hardware overhead. While it is known that a Geffe generator when used as a pattern generator for a built-in self-test, gives improved fault detection, the area overhead is sufficiently high for this not to be a practical approach. In this thesis, we propose three possible redesigns of the Geffe generator, and these redesigns are analyzed on both theoretical grounds and experiments. Our results show that two of our redesigned machines lead to fault coverage that is comparable to the original Geffe generator, but with very sharply reduced area overhead.
Download or read book Modified Geffe Test Pattern Generator for Built in Self test written by Dandan Qi and published by . This book was released on 2005 with total page 294 pages. Available in PDF, EPUB and Kindle. Book excerpt: Unlike linear Finite State Machines (FSM) such as Linear Feedback Shift Registers (LFSR), the Geffe generator, a nonlinear FSM, hasn't been frequently studied or used in the scenario of digital system testing. Such machines are used as pattern generators for built-in self-test. LFSRs have become widely used in today's integrated circuits since they have a comparatively low hardware overhead. While it is known that a Geffe generator when used as a pattern generator for a built-in self-test, gives improved fault detection, the area overhead is sufficiently high for this not to be a practical approach. In this thesis, we propose three possible redesigns of the Geffe generator, and these redesigns are analyzed on both theoretical grounds and experiments. Our results show that two of our redesigned machines lead to fault coverage that is comparable to the original Geffe generator, but with very sharply reduced area overhead.
Download or read book IEEE VLSI Test Symposium written by and published by . This book was released on 2001 with total page 464 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Sixth International Conferencew on Information Technology written by and published by Allied Publishers. This book was released on with total page 658 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Synthesis Techniques for Pseudo Random Built In Self Test written by Nur A. Touba and published by . This book was released on 1996 with total page 270 pages. Available in PDF, EPUB and Kindle. Book excerpt: Built-in self-test (BIST) techniques enable an integrated circuit (IC) to test itself. BIST reduces test and maintenance costs for an IC by eliminating the need for expensive test equipment and by allowing fast location of failed ICs in a system. BIST also allows an IC to be tested at its normal operating speed which is very important for detecting timing faults. Despite all of these advantages, BIST has seen limited use in industry because of area and performance overhead and increased design time. This dissertation presents automated techniques for implementing BIST in a way that minimizes area and performance overhead. A low-overhead approach for BIST is to use a linear feedback shift register (LFSR) to apply pseudorandom test patterns to the circuit-under-test. Unfortunately, many circuits contain random-pattern-resistant faults which limit the fault coverage that can be obtained for pseudo-random BIST. Several different approaches for solving this problem are presented. A logic synthesis procedure that performs testability-driven factoring to generate a random pattern testable design is presented. By considering random pattern testability during the factoring process, the overhead can be minimized. For hand-designed circuits or circuits that are not synthesizable, an innovative test point insertion procedure is described for inserting test points to make the circuit random pattern testable. A path tracing procedure is used for test point placement. A few of the existing primary inputs are ANDed together to form signals that drive the control points. These innovations result in fewer test points than previous methods. If it is not possible or not desirable to modify the circuit-under-test, then a procedure is described for synthesizing mapping logic that can placed at the output of the LFSR to transform the pseudorandom patterns so that they provide the required fault coverage. Much less overhead is required compared with weighted pattern testing methods. Lastly, a technique is described for placing bitfixing logic at the serial output of an LFSR to embed deterministic test patterns for the random pattern resistant faults in the pseudorandom bit sequence. This method does not require any performance overhead beyond what is needed for scan.
Download or read book System Level Validation written by Mingsong Chen and published by Springer Science & Business Media. This book was released on 2012-09-19 with total page 259 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.
Download or read book Boundary Scan Test written by Harry Bleeker and published by Springer Science & Business Media. This book was released on 2011-06-28 with total page 238 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ever-increasing miniaturization of digital electronic components is hampering the conventional testing of Printed Circuit Boards (PCBs) by means of bed-of-nails fixtures. Basically this is caused by the very high scale of integration of ICs, through which packages with hundreds of pins at very small pitches of down to a fraction of a millimetre, have become available. As a consequence the trace distances between the copper tracks on a printed circuit board cmne down to the same value. Not only the required small physical dimensions of the test nails have made conventional testing unfeasible, but also the complexity to provide test signals for the many hundreds of test nails has grown out of limits. Therefore a new board test methodology had to be invented. Following the evolution in the IC test technology. Boundary-Scan testing hm; become the new approach to PCB testing. By taking precautions in the design of the IC (design for testability), testing on PCB level can be simplified 10 a great extent. This condition has been essential for the success of the introduction of Boundary-Sc,m Test (BST) at board level.
Download or read book A Designer s Guide to Built In Self Test written by Charles E. Stroud and published by Springer Science & Business Media. This book was released on 2005-12-27 with total page 338 pages. Available in PDF, EPUB and Kindle. Book excerpt: A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.
Download or read book VLSI Test Principles and Architectures written by Laung-Terng Wang and published by Elsevier. This book was released on 2006-08-14 with total page 809 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Download or read book Combinational Test Generation for Sequential Circuits written by Yong Chang Kim and published by . This book was released on 2002 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Multichip Module Technology Handbook written by Philip E. Garrou and published by McGraw-Hill Professional Publishing. This book was released on 1998 with total page 696 pages. Available in PDF, EPUB and Kindle. Book excerpt: MCMs are electronic components that house multiple integrated circuits (ICs) upon a single chip. Their use in design allow systems that are faster, hotter and more reliable than those built with standalone ICs. More and more, the speed needs of electronic systems require MCMs. This comprehensive handbook aims to provide designers with the knowledge needed to understand and work with MCMs.
Download or read book Aliasing Reduction in Built in Self test microform written by Tracey May Bogue and published by National Library of Canada = Bibliothèque nationale du Canada. This book was released on 1996 with total page 122 pages. Available in PDF, EPUB and Kindle. Book excerpt: A major focus of the current research in testing is built-in self-test, or BIST. The standard BIST scheme consists of three main components: a test input generator, a circuit to be tested, and a compaction unit. The test sequence generated by the test input generator is applied to the circuit under test, and the output response from the tested circuit is compacted by the compaction unit into a signature. After the test, the resulting signature is compared to the correct one, and a fault is detected in the circuit under test if the two signatures are not identical. Aliasing occurs if a faulty output sequence from the circuit under test is compacted and produces the correct signature. In the past few years, the research and application of BIST techniques has increased significantly (2). In this thesis, the monitoring of built-in self-test by error detection circuitry is investigated. An existing method of constructing the error detection circuitry is evaluated through simulation experiments with benchmark circuits, and an alternative construction method is developed and evaluated. The testing of this error detection circuitry will also be considered, and an improved self-testing BIST scheme will be developed. In addition, the algebra of the multiple-input linear feedback shift register is analysed with respect to predicting the input sequences to the compaction unit which will be aliased. The use of MILFSR algebra to develop an improved low-overhead built-in self-test scheme is also considered; such a scheme would be independent of the circuit under test.
Download or read book Tenth International Conference on VLSI Design written by and published by . This book was released on 1997 with total page 612 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Automatic Test Pattern Generation Techniques for Built in Self test of Digital Circuits written by Dimitrios N. Kagaris and published by . This book was released on 1994 with total page 408 pages. Available in PDF, EPUB and Kindle. Book excerpt:
