Download or read book Low Power Techniques for CMOS Wireline Receivers written by Abishek Manian and published by . This book was released on 2016 with total page 130 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the ever-increasing need for high throughput from chip-to-chip I/Os, wireline transceivers are being pushed to operate at higher speeds. With the increase in data rates, the power consumption of broadband receivers has become critical in multi-lane applications like the Gigabit Ethernet. It is therefore desirable to minimize the power drawn by all of the building blocks. This work introduces a 40-Gb/s CMOS wireline receiver that advances the art by achieving a tenfold reduction in power and an efficiency of 0.35 mW/Gb/s. An innovative aspect of the proposed NRZ receiver is our "minimalist" approach, which recognizes that every additional stage in the data or clock path consumes more power and limits the bandwidth. The minimalist mentality avoids multiple stages in the front-end continuous-time linear equalizer (CTLE), quadrature oscillators in the clock and data recovery (CDR) circuit, clock or data buffers, or phase interpolation. Moreover, building blocks are shared among different functions so as to reduce the number of current paths between VDD and ground. Using charge-steering techniques extensively, the receiver contains only a few static bias currents adding up to about 6 mA. The minimalist approach also leads to a small footprint, about 110 um x 175 um, for the entire receiver, making it possible to design a multi-lane system in a small area and with short interconnects. This receiver incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer (DTLE) with 5.4-dB boost, a half-rate CDR circuit, a two-tap half-rate/quarter-rate decision-feedback equalizer, a 1:4 deserializer, and two new latch topologies. Since in recent designs, the CTLE draws significant power, this work introduces the DTLE as an efficient means of creating a high-frequency boost with only 0.3 mW. Fabricated in 45-nm CMOS technology, the receiver achieves a BER

Download or read book New Low Power Techniques for High Speed Wireline Receivers written by No Name Given Atharav and published by . This book was released on 2020 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the rapidly increasing Internet traffic and storage volume, the aggregate I/O bandwidth requirements in wireline systems have been climbing at a rate of approximately 2-3 times every two years. Thus, the power consumption of wireline transceivers has become increasingly more critical as higher data rates and a larger number of lanes per chip are sought. This issue is further intensified by the trade-offs between the channel loss and the power dissipation, especially in the receive path. While PAM4 signaling is attractive for lossier channels, it has mostly dictated receiver designs incorporating analog-to-digital converters (ADCs) with high power numbers. Non-return-to-zero (NRZ) receiver, on the other hand, can be realized in the analog domain, potentially consuming less power, but they must deal with a greater channel loss. This research introduces a 56-Gb/s NRZ receiver that draws 50 mW while exhibiting bit error rate (BER) of less than BER 10^(-12) for a channel loss of 25 dB at 28 GHz and 13.5 dB at 14 GHz. Such a receiver can compete with PAM4 counterparts and/or serve as part of 112-Gb/s systems that must also support 56-Gb/s NRZ reception. This work demonstrates a threefold improvement in the power efficiency.

Download or read book Low power Multi Gb s Wireline Communication written by Masum Hossain and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by Springer. This book was released on 2014-09-22 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).

Download or read book Low Power CMOS Design for Wireless Transceivers written by Alireza Zolfaghari and published by Springer Science & Business Media. This book was released on 2013-03-09 with total page 118 pages. Available in PDF, EPUB and Kindle. Book excerpt: This comprehensive treatment of the challenges in low-power RF CMOS design deals with the design and implementation of low- power wireless transceivers in a standard digital CMOS process. It addresses trade-offs and techniques that improve performance, from the component level to the architectural level.

Download or read book The Design and Implementation of Low Power CMOS Radio Receivers written by Derek Shaeffer and published by Springer Science & Business Media. This book was released on 2007-05-08 with total page 208 pages. Available in PDF, EPUB and Kindle. Book excerpt: It is hardly a profound observation to note that we remain in the midst of a wireless revolution. In 1998 alone, over 150 million cell phones were sold worldwide, representing an astonishing 50% increase over the previous year. Maintaining such a remarkable growth rate requires constant innovation to decrease cost while increasing performance and functionality. Traditionally, wireless products have depended on a mixture of semicond- tor technologies, spanning GaAs, bipolar and BiCMOS, just to name a few. A question that has been hotly debated is whether CMOS could ever be suitable for RF applications. However, given the acknowledged inferiority of CMOS transistors relative to those in other candidate technologies, it has been argued by many that “CMOS RF” is an oxymoron, an endeavor best left cloistered in the ivory towers of academia. In rebuttal, there are several compelling reasons to consider CMOS for wi- less applications. Aside from the exponential device and density improvements delivered regularly by Moore’s law, only CMOS offers a technology path for integrating RF and digital elements, potentially leading to exceptionally c- pact and low-cost devices. To enable this achievement, several thorny issues need to be resolved. Among these are the problem of poor passive com- nents, broadband noise in MOSFETs, and phase noise in oscillators made with CMOS. Beyond the component level, there is also the important question of whether there are different architectural choices that one would make if CMOS were used, given the different constraints.

Download or read book Design Techniques for High speed Low power Wireline Receivers written by Arash Zargaran Yazd and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Wake up Receiver Based Ultra Low Power WBAN written by Maarten Lont and published by Springer. This book was released on 2014-05-28 with total page 158 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents the cross-layer design and optimization of wake-up receivers for wireless body area networks (WBAN), with an emphasis on low-power circuit design. This includes the analysis of medium access control (MAC) protocols, mixer-first receiver design, and implications of receiver impairments on wideband frequency-shift-keying (FSK) receivers. Readers will learn how the overall power consumption is reduced by exploiting the characteristics of body area networks. Theoretical models presented are validated with two different receiver implementations, in 90nm and 40nm CMOS technology.

Download or read book Low Power RF Circuit Design in Standard CMOS Technology written by Unai Alvarado and published by Springer Science & Business Media. This book was released on 2011-10-18 with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

Download or read book Ultra Low Power and Ultra Low Cost Short Range Wireless Receivers in Nanoscale CMOS written by Zhicheng Lin and published by Springer. This book was released on 2015-07-25 with total page 119 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides readers with a state-of-the-art description of techniques to be used for ultra-low-power (ULP) and ultra-low-cost (ULC), short-range wireless receivers. Readers will learn what is required to deploy these receivers in short-range wireless sensor networks, which are proliferating widely to serve the internet of things (IoT) for “smart cities.” The authors address key challenges involved with the technology and the typical tradeoffs between ULP and ULC. Three design examples with advanced circuit techniques are described in order to address these trade-offs, which special focus on cost minimization. These three techniques enable respectively, cascading of radio frequency (RF) and baseband (BB) circuits under an ultra-low-voltage (ULV) supply, cascading of RF and BB circuits in current domain for current reuse and a novel function-reuse receiver architecture, suitable for ULV and multi-band ULP applications such as the sub-GHz ZigBee.

Download or read book The Design and Implementation of Low Power CMOS Radio Receivers written by Derek Shaeffer and published by Taylor & Francis US. This book was released on 1999-05-31 with total page 1 pages. Available in PDF, EPUB and Kindle. Book excerpt: The primary goal of The Design and Implementation of Low-Power CMOS Radio Receivers is to explore techniques for implementing wireless receivers in an inexpensive complementary metal-oxide-semiconductor (CMOS) technology. Although the techniques developed apply somewhat generally across many classes of receivers, the specific focus of this work is on the Global Positioning System (GPS). Because GPS provides a convenient vehicle for examining CMOS receivers, a brief overview of the GPS system and its implications for consumer electronics is presented. The GPS system comprises 24 satellites in low earth orbit that continuously broadcast their position and local time. Through satellite range measurements, a receiver can determine its absolute position and time to within about 100m anywhere on Earth, as long as four satellites are within view. The deployment of this satellite network was completed in 1994 and, as a result, consumer markets for GPS navigation capabilities are beginning to blossom. Examples include automotive or maritime navigation, intelligent hand-off algorithms in cellular telephony, and cellular emergency services, to name a few. Of particular interest in the context of this book are embedded GPS applications where a GPS receiver is just one component of a larger system. Widespread proliferation of embedded GPS capability will require receivers that are compact, cheap and low-power. The Design and Implementation of Low-Power CMOS Radio Receivers will be of interest to professional radio engineers, circuit designers, professors and students engaged in integrated radio research and other researchers who work in the radio field.

Download or read book High Speed CMOS Circuits for Optical Receivers written by Jafar Savoj and published by Springer Science & Business Media. This book was released on 2001-05-31 with total page 132 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the exponential growth of the number of Internet nodes, the volume of the data transported on the backbone has increased with the same trend. The load of the global Internet backbone will soon increase to tens of terabits per second. This indicates that the backbone bandwidth requirements will increase by a factor of 50 to 100 every seven years. Transportation of such high volumes of data requires suitable media with low loss and high bandwidth. Among the available transmission media, optical fibers achieve the best performance in terms of loss and bandwidth. High-speed data can be transported over hundreds of kilometers of single-mode fiber without significant loss in signal integrity. These fibers progressively benefit from reduction of cost and improvement of perf- mance. Meanwhile, the electronic interfaces used in an optical network are not capable of exploiting the ultimate bandwidth of the fiber, limiting the throughput of the network. Different solutions at both the system and the circuit levels have been proposed to increase the data rate of the backbone. System-level solutions are based on the utilization of wave-division multiplexing (WDM), using different colors of light to transmit s- eral sequences simultaneously. In parallel with that, a great deal of effort has been put into increasing the operating rate of the electronic transceivers using highly-developed fabrication processes and novel c- cuit techniques.

Download or read book Wideband CMOS Receivers written by Miguel D. Fernandes and published by Springer. This book was released on 2015-07-10 with total page 115 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology. The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

Download or read book CMOS Receiver Front ends for Gigabit Short Range Optical Communications written by Francisco Aznar and published by Springer Science & Business Media. This book was released on 2012-08-09 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints. These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip. The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length. This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level.

Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by . This book was released on 2014-10-31 with total page 172 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Architectures and Circuit Design Techniques for Ultra Low Voltage CMOS Receivers written by Ajay Balankutty and published by . This book was released on 2010 with total page 336 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book VLSI SoC Design Trends written by Andrea Calimera and published by Springer Nature. This book was released on 2021-07-14 with total page 372 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.