Download or read book Low power High speed High resolution Delta sigma Modulators for Digital TV Receivers in Nanometer CMOS written by Mostafa Haroun and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: "The use of high-speed high-resolution analog-to-digital converters (ADCs) allows part of the signal processing to be done in the digital domain allowing for higher system integration and cheaper fabrication. Becoming more in use, hand-held devices have low-power requirements to allow for longer battery life. Also, designing ADCs in nanometer digital CMOS technologies make them more integrable with digital processing blocks and cheaper. This thesis aims at designing a high-speed (16MS/s conversion rate) high-resolution (12bits) Delta-Sigma modulator with low-power consumption in nanometer CMOS. Delta-Sigma modulators can achieve high resolution in low and medium speed applications. For higher speed applications, the oversampling ratio (OSR) will have to be kept low to avoid inefficient design. However, lowering the OSR requires special care in the design starting from the architecture until the full circuit implementation. In nanometer CMOS technologies, analog properties, such as intrinsic gain, degrade which might result in a higher power consumption. Moreover, the low nominal supply voltages associated with such technologies adds more challenges to the design of a low distortion power-efficient Delta-Sigma modulator. Targeting a specic resolution, lowering the voltage supply usually results in a higher power consumption. This thesis suggests possible solutions to achieve low power consumption while targeting high-speed applications in nanometer low-voltage-supply environment.This thesis presents a low-power Discrete-Time (DT) Delta-Sigma modulator making use of a single-loop multibit DT digital input-feedforward Delta-Sigma architecture. The main feature of this architecture is the reduced signal swings at the output of the integrators which allows the use of a low voltage supply. The low-power Switched-Capacitor (SC) implementation is ensured by using a novel opamp switching technique, optimizing simultaneous opamp's settling in cascaded nondelaying SC integrators, and using non-overlapping clock phases with unequal duty-cycles. The novel opamp switching technique is based on a current-mirror opamp with switchable transconductances. The current-mirror opamp works with full current during the charge-transfer phase while the output current is partially switched off during the sampling phase. Power saving can be achieved while ensuring that the opamp output is available during both phases. The simultaneous settling of series opamps in a two cascaded nondelaying SC integrators scheme is looked at as a two-pole system where power optimization is necessary to ensure minimum power consumption while meeting the settling requirements. The use of clock phases with unequal duty-cycles gives the designer an extra degree of freedom to further power optimize the design. The experimental Delta-Sigma ADC is a 4th-order 5.5bits single-loop Delta-Sigma modulator with an OSR of 8. The design starts with the structural-level aspects in which system-level decisions are made and simulations are carried-out with behavioral models to find the suitable circuit parameters. Circuit-level design in then considered to design each block and simulate the full-system. Fabricated in 1V 65nm CMOS, the Delta-Sigma modulator prototype occupies an active area of 1.2mm2. Although the targeted resolution is about 12bits, the experimental results shows a dynamic range (DR) of 66dB (11bits) over an 8MHz bandwidth while consuming 26mW and a peak SNR/SNDR of 64/58.5dB. The proposed opamp switching technique brings the total power consumption from 29mW to 26mW without affecting the performance (SNDR stays at 58.5dB). The deviation in experimental performance, from simulations, in thought to be due to higher parasitic capacitance requiring higher bias currents which results in drop of opamp dc gain. Compared to state of the art high-speed high-resolution Delta-Sigma modulators operated from 1V supply and fabricated in CMOS, it achieves a reasonable Figure-of-Merit." --

Download or read book The Design of Low Voltage Low Power Sigma Delta Modulators written by Shahriar Rabii and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 198 pages. Available in PDF, EPUB and Kindle. Book excerpt: Oversampling techniques based on sigma-delta modulation are widely used to implement the analog/digital interfaces in CMOS VLSI technologies. This approach is relatively insensitive to imperfections in the manufacturing process and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in the low-voltage environment that is increasingly demanded by advanced VLSI technologies and by portable electronic systems. In The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, an analysis of power dissipation in sigma-delta modulators is presented, and a low-voltage implementation of a digital-audio performance A/D converter based on the results of this analysis is described. Although significant power savings can typically be achieved in digital circuits by reducing the power supply voltage, the power dissipation in analog circuits actually tends to increase with decreasing supply voltages. Oversampling architectures are a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison with Nyquist-rate converters. In fact, it is shown that the power dissipation of a sigma-delta modulator can approach that of a single integrator with the resolution and bandwidth required for a given application. In this research the influence of various parameters on the power dissipation of the modulator has been evaluated and strategies for the design of a power-efficient implementation have been identified. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators begins with an overview of A/D conversion, emphasizing sigma-delta modulators. It includes a detailed analysis of noise in sigma-delta modulators, analyzes power dissipation in integrator circuits, and addresses practical issues in the circuit design and testing of a high-resolution modulator. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators will be of interest to practicing engineers and researchers in the areas of mixed-signal and analog integrated circuit design.

Download or read book Continuous Time Delta Sigma Modulators for High Speed A D Conversion written by James A. Cherry and published by Springer Science & Business Media. This book was released on 2006-04-18 with total page 272 pages. Available in PDF, EPUB and Kindle. Book excerpt: Among analog-to-digital converters, the delta-sigma modulator has cornered the market on high to very high resolution converters at moderate speeds, with typical applications such as digital audio and instrumentation. Interest has recently increased in delta-sigma circuits built with a continuous-time loop filter rather than the more common switched-capacitor approach. Continuous-time delta-sigma modulators offer less noisy virtual ground nodes at the input, inherent protection against signal aliasing, and the potential to use a physical rather than an electrical integrator in the first stage for novel applications like accelerometers and magnetic flux sensors. More significantly, they relax settling time restrictions so that modulator clock rates can be raised. This opens the possibility of wideband (1 MHz or more) converters, possibly for use in radio applications at an intermediate frequency so that one or more stages of mixing might be done in the digital domain. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits covers all aspects of continuous-time delta-sigma modulator design, with particular emphasis on design for high clock speeds. The authors explain the ideal design of such modulators in terms of the well-understood discrete-time modulator design problem and provide design examples in Matlab. They also cover commonly-encountered non-idealities in continuous-time modulators and how they degrade performance, plus a wealth of material on the main problems (feedback path delays, clock jitter, and quantizer metastability) in very high-speed designs and how to avoid them. They also give a concrete design procedure for a real high-speed circuit which illustrates the tradeoffs in the selection of key parameters. Detailed circuit diagrams, simulation results and test results for an integrated continuous-time 4 GHz band-pass modulator for A/D conversion of 1 GHz analog signals are also presented. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits concludes with some promising modulator architectures and a list of the challenges that remain in this exciting field.

Download or read book High Speed and Wide Bandwidth Delta Sigma ADCs written by Muhammed Bolatkale and published by Springer. This book was released on 2014-06-06 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nano meter-CMOS processes. The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators. Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.

Download or read book Top Down Design of High Performance Sigma Delta Modulators written by Fernando Medeiro and published by Springer Science & Business Media. This book was released on 2013-04-18 with total page 303 pages. Available in PDF, EPUB and Kindle. Book excerpt: The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.

Download or read book High Efficiency Wideband Low power Delta sigma Modulators written by Sang Hyeon Lee and published by . This book was released on 2012 with total page 91 pages. Available in PDF, EPUB and Kindle. Book excerpt: Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two architectural innovations and a development and realization of a state-of-the-art delta-sigma analog to digital converter with effective design techniques in both architectural and circuit levels are presented. The first one is timing-relaxed double noise coupling which effectively provides 2nd order noise shaping in the noise transfer function and overcomes stringent timing requirement for quantization and DEM. The second one presented is a noise shaping SAR quantizer, which provides one order of noise shaping in the noise transfer function. It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion delta-sigma modulator which is suitable for adopting SAR quantizer. Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for WLAN applications is presented. It uses a noise folding free double sampling technique and an improved low-distortion architecture with an embedded-adder integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18[micro]m CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27 pJ/conv-step. The measurement results indicate that the proposed design ideas are effective and useful for wideband, low power delta-sigma analog-to-digital converters with low oversampling ratio.

Download or read book Design Techniques for Mash Continuous Time Delta Sigma Modulators written by Qiyuan Liu and published by Springer. This book was released on 2018-03-27 with total page 215 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-ΔΣM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

Download or read book Sigma Delta Converters Practical Design Guide written by Jose M. de la Rosa and published by John Wiley & Sons. This book was released on 2018-08-22 with total page 892 pages. Available in PDF, EPUB and Kindle. Book excerpt: Thoroughly revised and expanded to help readers systematically increase their knowledge and insight about Sigma-Delta Modulators Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), Σ∆Ms cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications. Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators—from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art Σ∆Ms. It makes more emphasis on two key points, which were not treated so deeply in the first edition: It includes a more detailed explanation of Σ∆Ms implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations. It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of Σ∆ converters. Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style.

Download or read book Power Efficient Continuous time Delta sigma Modulator Architectures for Wideband Analog to Digital Conversion written by Mohammad Ranjbar and published by . This book was released on 2012 with total page 206 pages. Available in PDF, EPUB and Kindle. Book excerpt: This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.

Download or read book Robust Sigma Delta Converters written by Robert H.M. van Veldhoven and published by Springer Science & Business Media. This book was released on 2011-01-30 with total page 306 pages. Available in PDF, EPUB and Kindle. Book excerpt: Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC. The book proposes to categorize these requirements in 5 quality indicators which can be used to qualify a system, namely accuracy, robustness, flexibility, efficiency and emission. In the book these quality indicators are used to categorize Sigma Delta converter theory. A few highlights on each of these quality indicators are; Quality indicators: provide a means to quantify system quality. Accuracy: introduction of new Sigma Delta Modulator architectures. Robustness: a significant extension on clock jitter theory based on phase and error amplitude error models. Extension of the theory describing aliasing in Sigma Delta converters for different types of DACs in the feedback loop. Flexibility: introduction of a Sigma Delta converter bandwidth scaling theory leading to very flexible Sigma Delta converters. Efficiency: introduction of new Figure-of-Merits which better reflect performance-power trade-offs. Emission: analysis of Sigma Delta modulators on emission is not part of the book The quality indicators also reveal that, to exploit nowadays advanced IC technologies, things should be done as much as possible digital up to a limit where system optimization allows reducing system margins. At the end of the book Sigma Delta converter implementations are shown which are digitized on application-, architecture-, circuit- and layout-level. Robust Sigma Delta Converters is written under the assumption that the reader has some background in receivers and in A/D conversion.

Download or read book Continuous Time Sigma Delta Modulation for A D Conversion in Radio Receivers written by Lucien Breems and published by Springer Science & Business Media. This book was released on 2006-04-18 with total page 165 pages. Available in PDF, EPUB and Kindle. Book excerpt: This text describes the design and theory of continuous-time sigma-delta modulators for analogue-to-digital conversion in radio receivers. The book's main focus is on dynamic range, linearity and power efficiency aspects of sigma-delta modulators, which are very important requirements for use in battery operated receivers.

Download or read book Wide bandwidth High resolution Delta sigma Analog to digital Converters written by Ramin Zanbaghi and published by . This book was released on 2011 with total page 115 pages. Available in PDF, EPUB and Kindle. Book excerpt: There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in [delta sigma] modulators is a new stage-sharing technique in a discrete-time 2-2 MASH [delta sigma] ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power.

Download or read book Low power Double sampled Delta sigma Modulator for Broadband Applications written by Weilun Shen and published by . This book was released on 2011 with total page 202 pages. Available in PDF, EPUB and Kindle. Book excerpt: High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance delta-sigma ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled delta-sigma modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization. Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion delta-sigma modulator. A second-order delta-sigma modulator was designed and simulated to verify the proposed modulator topology. Finally, design of a double-sampled broadband 12-bit delta-sigma modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques: 1. Double sampled integrator to increase the effective over-sampling ratio. 2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back. A 2+2 cascaded topology with 3-bit internal quantizer is used in this delta-sigma modulator to adequately suppress the quantization noise while guarantee the loop stability. This delta-sigma modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm2 and consumes 10mW with a supply voltage of 1.2V.

Download or read book Delta sigma Data Converters for Broadband Digital Communications written by Anas A. Hamoui and published by . This book was released on 2004 with total page 318 pages. Available in PDF, EPUB and Kindle. Book excerpt: Accordingly, to meet the stringent ADC specifications imposed by emerging broadband communication applications, this thesis explores the following: (1) High-Speed High-Resolution Delta-Sigma (DeltaSigma) ADCs: Oversampling DeltaSigma ADCs can achieve a high-resolution data conversion in low-speed applications using low-accuracy analog components. However, extending these ADCs to high-speed applications requires lowering the oversampling ratio (OSR), due to both power and CMOS technology limitations. Unfortunately, this significantly limits the efficiency of a DeltaSigma ADC in achieving a high-resolution analog/digital (A/D) conversion. Therefore, this thesis presents several techniques to enable the OSR lowering in high-speed DeltaSigma ADCs without compromising the resolution. Specifically, a low-distortion single-stage architecture is proposed for high-order multibit DeltaSigma modulators. Furthermore, a dynamic-element-matching (DEM) technique, called Pseudo Data-Weighted-Averaging (Pseudo DWA), with reduced tone behavior at a low OSR is proposed for the linearization of the digital-to-analog converter (DAC) in a multibit DeltaSigma modulator. (2) Low-Voltage Switched-Capacitor (SC) Circuit Implementation: To demonstrate the practicality of the proposed modulator architecture and DAC-linearization technique when the OSR and the supply voltage are limited by the technology, a DeltaSigma modulator prototype is designed using SC circuit techniques and fabricated in a 0.18-mum standard digital CMOS process. When operated from a 1.8-V supply, it achieves a 13-bit spurious-free dynamic range (SFDR) and a 12-bit signal-to-noise ratio (SNR) over a 3-MS/s conversion bandwidth with a 1.85-V pp input-signal range. The analog and digital power consumptions are, respectively, 32.4 mW and 12.6 mW. The on-chip references dissipate 14.4 mW. Accordingly, this DeltaSigma modulator was one of the few early-reported CMOS DeltaSigma modulators targeting high-speed (& ge;2 MS/s) high-resolution (& ge;12 bits) applications and operating from a low supply voltage (& le;1.8 V). Furthermore, its measured performance compared favourably to the previously-reported state-of-the-art DeltaSigma modulators. Ironically, the significance of analog integrated-circuit design is growing more prominent in today's "digital" communication age due, in part, to data converters. Specifically, the proliferation of broadband digital communication applications is stimulating the evolving research towards the development of analog-to-digital converters (ADCs) with higher speeds and higher resolutions. These ADCs must be implemented in standard digital CMOS processes for higher system integration and lower fabrication costs. However, in nano-scale CMOS technologies, the decreasing supply voltages and the shrinking devices with poor analog-processing capabilities complicate the low-power design of high-resolution analog circuits.

Download or read book Low voltage Low power CMOS Sigma delta Modulators for High resolution A D Conversion written by Hyunsik Park and published by . This book was released on 2008 with total page 153 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book High speed Delta sigma Data Converters for Next generation Wireless Communication written by Sakkarapani Balagopal and published by . This book was released on 2014 with total page 179 pages. Available in PDF, EPUB and Kindle. Book excerpt: "In recent years, Continuous-time Delta-Sigma(CT-[delta][sigma]) analog-to-digital converters (ADCs) have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths greater than 15 MHz and higher resolution of 10 to 14 bits. This dissertation investigates the current state-of-the-art high-speed single-bit and multi-bit Continuous-time Delta-Sigma modulator (CT-[delta][sigma]M) designs and their limitations due to circuit non-idealities in achieving the performance required for next-generation wireless standards. Also, we presented complete architectural and circuit details of a high-speed single-bit and multi-bit CT-[delta][sigma]M operating at a sampling rate of 1.25 GSps and 640 MSps respectively (the highest reported sampling rate in a 0.13 [mu]m CMOS technology node) with measurement results. Further, we propose novel hybrid [delta][sigma] architecture with two-step quantizer to alleviate the bandwidth and resolution bottlenecks associated with the contemporary CT-[delta][sigma]M topologies. To facilitate the design with the proposed architecture, a robust systematic design method is introduced to determine the loop-filter coefficients by taking into account the non-ideal integrator response, such as the finite opamp gain and the presence of multiple parasitic poles and zeros. Further, comprehensive system-level simulation is presented to analyze the effect of two-step quantizer non-idealities such as the offset and gain error in the sub-ADCs, and the current mismatch between the MSB and LSB elements in the feedback DAC. The proposed novel architecture is demonstrated by designing a high-speed wideband 4th order CT-[delta][sigma] modulator prototype, employing a two-step quantizer with 5-bits resolution. The proposed modulator takes advantage of the combination of a high-resolution two-step quantization technique and an excess-loop delay (ELD) compensation of more than one clock cycle to achieve lower-power consumption (28 mW), higher dynamic range (>69 dB) with a wide conversion bandwidth (20 MHz), even at a lower sampling rate of 400 MHz. The proposed modulator achieves a Figure of Merit (FoM) of 340 fJ/level."--Boise State University ScholarWorks.

Download or read book Sigma Delta Modulators written by Søren Hein and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 259 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog-to-digital (A/D) converters are key components in digital signal processing (DSP) systems and are therefore receiving much attention as DSP becomes increasingly prevalent in telephony, audio, video, consumer products, etc. The varying demands on conversion rate, resolution and other characteristics have inspired a large number of competing A/D conversion techniques. Sigma Delta Modulators: Nonlinear Decoding Algorithms and Stability Analysis is concerned with the particular class of A/D techniques called oversampled noise-shaping (ONS) that has recently come into prominence for a number of applications. The popularity of ONS converters is due to their ease of implementation and robustness to circuit imperfectors. An ONS converter consists of an encoder that generates a high-rate, low-resolution digital signal, and a decoder that produces a low-rate, high-resolution digital approximation to the analog encoder input. The conventional decoding approach is based on linear filtering. Sigma Delta Modulators presents the optimal design of an ONS decoder for a given encoder. It is shown that nonlinear decoding can achieve gains in signaling ratio and the encoder architecture. The book then addresses the instability problem that plagues higher-order ONS encoders. A new stability concept is introduced that is well-suited to ONS encoders, and it is applied to the double-loop encoder as well as to the class of interpolative encoders. It is shown that there exists a trade-off between stability and SNR performance. Based on the results, explicit design examples are presented. Sigma Delta Modulators: Nonlinear Decoding Algorithms and Stability Analysis is a valuable reference source for researchers and engineers in industry and academia working on or interested in design and analysis of A/D converters, particularly to those working in quantization theory and signal reconstruction, and can serve as a text for advanced courses on the subjects treated.