Download or read book VLSI Fault Modeling and Testing Techniques written by George W. Zobrist and published by Praeger. This book was released on 1993 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Download or read book Testing Static Random Access Memories written by Said Hamdioui and published by Springer Science & Business Media. This book was released on 2013-06-29 with total page 231 pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.
Download or read book Assessing Fault Model and Test Quality written by Kenneth M. Butler and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt: For many years, the dominant fault model in automatic test pattern gen eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.
Download or read book Fault Models in Testing written by Gregor von Bochmann and published by . This book was released on 1991 with total page 28 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "The testing of implementations in order to check their validity is important during the development of communication protocols, as in the more general areas of hardware and software development. Protocol testing methods have profited from experience in hardware and software testing; in addition, much recent work considers testing based on finite state machine models. This paper points out the similarities between testing of hardware, software, and communication protocols in the context of a general testing framework and the use of fault models. Fault models not only provide a basis for the definition of test coverage measures, but also lead to methodologies for test suite design and test result analysis for diagnosis. While the principles of fault models are essentially the same in the different areas of hardware, software and protocols, the particular fault models that can be applied depend on the specification formalism used to describe the implementation under test. The paper presents various fault models corresponding to hardware, software, finite state machines and several other modelling techniques, including Formal Description Techniques."
Download or read book High Performance Memory Testing written by R. Dean Adams and published by Springer Science & Business Media. This book was released on 2005-12-29 with total page 252 pages. Available in PDF, EPUB and Kindle. Book excerpt: Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.
Download or read book Models in Hardware Testing written by Hans-Joachim Wunderlich and published by Springer Science & Business Media. This book was released on 2009-11-12 with total page 263 pages. Available in PDF, EPUB and Kindle. Book excerpt: Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Download or read book Data Driven and Model Based Methods for Fault Detection and Diagnosis written by Majdi Mansouri and published by Elsevier. This book was released on 2020-02-05 with total page 322 pages. Available in PDF, EPUB and Kindle. Book excerpt: Data-Driven and Model-Based Methods for Fault Detection and Diagnosis covers techniques that improve the quality of fault detection and enhance monitoring through chemical and environmental processes. The book provides both the theoretical framework and technical solutions. It starts with a review of relevant literature, proceeds with a detailed description of developed methodologies, and then discusses the results of developed methodologies, and ends with major conclusions reached from the analysis of simulation and experimental studies. The book is an indispensable resource for researchers in academia and industry and practitioners working in chemical and environmental engineering to do their work safely. Outlines latent variable based hypothesis testing fault detection techniques to enhance monitoring processes represented by linear or nonlinear input-space models (such as PCA) or input-output models (such as PLS) Explains multiscale latent variable based hypothesis testing fault detection techniques using multiscale representation to help deal with uncertainty in the data and minimize its effect on fault detection Includes interval PCA (IPCA) and interval PLS (IPLS) fault detection methods to enhance the quality of fault detection Provides model-based detection techniques for the improvement of monitoring processes using state estimation-based fault detection approaches Demonstrates the effectiveness of the proposed strategies by conducting simulation and experimental studies on synthetic data
Download or read book Advanced Test Methods for SRAMs written by Alberto Bosio and published by Springer Science & Business Media. This book was released on 2009-10-08 with total page 179 pages. Available in PDF, EPUB and Kindle. Book excerpt: Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.
Download or read book Introduction to IDDQ Testing written by S. Chakravarty and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 336 pages. Available in PDF, EPUB and Kindle. Book excerpt: Testing techniques for VLSI circuits are undergoing many exciting changes. The predominant method for testing digital circuits consists of applying a set of input stimuli to the IC and monitoring the logic levels at primary outputs. If, for one or more inputs, there is a discrepancy between the observed output and the expected output then the IC is declared to be defective. A new approach to testing digital circuits, which has come to be known as IDDQ testing, has been actively researched for the last fifteen years. In IDDQ testing, the steady state supply current, rather than the logic levels at the primary outputs, is monitored. Years of research suggests that IDDQ testing can significantly improve the quality and reliability of fabricated circuits. This has prompted many semiconductor manufacturers to adopt this testing technique, among them Philips Semiconductors, Ford Microelectronics, Intel, Texas Instruments, LSI Logic, Hewlett-Packard, SUN microsystems, Alcatel, and SGS Thomson. This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers. Introduction to IDDQ Testing is designed to educate this community. The authors have summarized in one volume the main findings of more than fifteen years of research in this area.
Download or read book A New Class of Fault Models and Test Algorithms for Dual port Dynamic RAM Testing written by V. Castro Alves and published by . This book was released on 1994 with total page 6 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Models in Hardware Testing written by Hans-Joachim Wunderlich and published by Springer. This book was released on 2010-04-29 with total page 257 pages. Available in PDF, EPUB and Kindle. Book excerpt: Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Download or read book Lifetime Validation of Digital Systems Via Fault Modeling and Test Generation written by Hussain Said Al-Asaad and published by . This book was released on 1998 with total page 330 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Software Fault Detection and Correction Modeling and Applications written by Rui Peng and published by Springer. This book was released on 2018-11-01 with total page 117 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book focuses on software fault detection and correction processes, presenting 5 different paired models introduced over the last decade and discussing their applications, in particular to determining software release time. The first work incorporates the testing effort function and the fault introduction process into the paired fault detection and fault correction models. The second work incorporates fault dependency, while the third adopts a Markov approach for studying fault detection and correction processes. The fourth work considers the multi-release property of various software, and models fault detection and correction processes. The last work classifies faults into four types and models the fault-detection and correction processes. Enabling readers to familiarize themselves with how software reliability can be modeled when different factors need to be considered, and how the approaches can be used to analyze other systems, the book is important reference guide for researchers in the field of software reliability engineering and practitioners working on software projects. To gain the most from the book, readers should have a firm grasp of the fundamentals of the stochastic process.
Download or read book Hierarchical Modeling for VLSI Circuit Testing written by Debashis Bhattacharya and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Download or read book Testing of Digital Systems written by N. K. Jha and published by Cambridge University Press. This book was released on 2003-05-08 with total page 1016 pages. Available in PDF, EPUB and Kindle. Book excerpt: Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide-ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through every key area, including detailed treatment of the latest techniques such as system-on-a-chip and IDDQ testing. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Download or read book Analog fault models for mixed integrated circuit testing written by Anne Meixner and published by . This book was released on 1993 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
