Download or read book Fabrication of High Performance Ge MOS Devices by Integrating Novel Surface Passivation and Crystalline High Gate Dielectric written by 吳旻霖 and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Surface Passivation and Junction Engineering in Silicon written by Gaurav Thareja and published by Stanford University. This book was released on 2011 with total page 99 pages. Available in PDF, EPUB and Kindle. Book excerpt: The planar silicon MOSFET is facing diminishing performance returns in improvement from device geometry scaling. Two alternative devices are being explored as possible solutions to this problem. The first contender is a multi-gate device (FINFET or surround gate) and the other is a MOSFET with high mobility channel material such as germanium, III-V or carbon. Ge has emerged as an important materials platform during recent years. With its high carrier mobility and the ability to detect and emit photons at telecommunications wavelengths, Ge is an attractive candidate for applications in both high performance electronics and optoelectronics. Moreover due to its compatibility with conventional CMOS fabrication, it can be processed using the standard manufacturing techniques that are currently used for silicon. However Ge does present a number of unique challenges that must be overcome, including issues of surface passivation, low n-type dopant solubility, and high dopant diffusivity. In this work, the unique properties of surface passivation enabled by radical oxidation are discussed. Some of the highlights are low temperature processing, substrate orientation independent growth rate of dielectric and low interface density. Subsequently, this radical oxidation is applied to 3D vertical gate all around (GAA) silicon MOSFET devices. Higher drive current, lower gate leakage and higher gate dielectric breakdown voltage are demonstrated for GAA devices using radical oxidation in comparison to thermal oxidation In the second part, radical oxidation is investigated for GeO2 growth as an interfacial layer in high-k / Ge gate stack. Using MOSCAP and n-MOSFET devices on Ge, low interface state density combined with drive current and electron mobility enhancement is demonstrated for Ge devices. In the third part, the source/drain junctions for Ge are studied. Ultra-shallow junctions using plasma immersion ion implantation are demonstrated. High n-type dopant activation in Ge using laser annealing is realized along with high performance diodes, significant reduction of contact resistance and integration in a MOSFET process flow.

Download or read book Interface engineered Ge MOSFETs for Future High Performance CMOS Applications written by Duygu Kuzum and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, introduction of performance boosters like novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS. Detailed characterization of gate dielectric/channel interface and a deeper understanding of mobility degradation mechanisms are needed to address the Ge NMOS performance problem and to improve PMOS performance. In the first part of this dissertation, the electrical characterization results on Ge NMOS and PMOS devices fabricated with GeON gate dielectric are presented. Carrier scattering mechanisms are studied through low temperature mobility measurements. For the first time, the effect of substrate crystallographic orientation on inversion electron and hole mobilities is investigated. Direct formation of a high-k dielectric on Ge has not given good results in the past. A good quality interface layer is required before the deposition of a high-K dielectric. In the second part of this dissertation, ozone-oxidation process is introduced to engineer Ge/insulator interface. Electrical and structural characterizations and stability analysis are carried out and high quality Ge/dielectric interface with low interface trap density is demonstrated. Detailed extraction of interface trap density distribution across the bandgap and close to band edges of Ge, using low temperature conductance and capacitance measurements is presented. Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups worldwide. In spite of the increasing interest in Ge, the major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In the last part of this dissertation, the results on Ge NMOS devices fabricated with the ozone-oxidation and the low temperature source/drain activation processes are discussed. These devices achieve the highest electron mobility to-date, about 1.5 times the universal Si mobility. Detailed interface characterizations, trapping analyses and gated Hall device measurements are performed to identify the mechanisms behind poor Ge NMOS performance in the past.

Download or read book Gate Dielectrics and MOS ULSIs written by Takashi Hori and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 362 pages. Available in PDF, EPUB and Kindle. Book excerpt: Gate Dielectrics and MOS ULSIs provides necessary and sufficient information for those who wish to know well and go beyond the conventional SiO2 gate dielectric. The topics particularly focus on dielectric films satisfying the superior quality needed for gate dielectrics even in large-scale integration. And since the quality requirements are rather different between device applications, they are selected in an applicatipn-oriented manner, e.g., conventional SiO2 used in CMOS logic circuits, nitrided oxides, which recently became indispensable for flash memories, and composite ONO and ferroelectric films for passive capacitors used in DRAM applications. The book also covers issues common to all gate dielectrics, such as MOSFET physics, evaluation, scaling, and device application/integration for successful development. The information is as up to date as possible, especially for nanometer-range ultrathin gate-dielectric films indispensible in submicrometer ULSIs. The text together with abundant illustrations will take even the inexperienced reader up to the present high state of the art. It is the first book presenting nitrided gate oxides in detail.

Download or read book Surface Passivation and Junction Engineering in Silicon written by Gaurav Thareja and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The planar silicon MOSFET is facing diminishing performance returns in improvement from device geometry scaling. Two alternative devices are being explored as possible solutions to this problem. The first contender is a multi-gate device (FINFET or surround gate) and the other is a MOSFET with high mobility channel material such as germanium, III-V or carbon. Ge has emerged as an important materials platform during recent years. With its high carrier mobility and the ability to detect and emit photons at telecommunications wavelengths, Ge is an attractive candidate for applications in both high performance electronics and optoelectronics. Moreover due to its compatibility with conventional CMOS fabrication, it can be processed using the standard manufacturing techniques that are currently used for silicon. However Ge does present a number of unique challenges that must be overcome, including issues of surface passivation, low n-type dopant solubility, and high dopant diffusivity. In this work, the unique properties of surface passivation enabled by radical oxidation are discussed. Some of the highlights are low temperature processing, substrate orientation independent growth rate of dielectric and low interface density. Subsequently, this radical oxidation is applied to 3D vertical gate all around (GAA) silicon MOSFET devices. Higher drive current, lower gate leakage and higher gate dielectric breakdown voltage are demonstrated for GAA devices using radical oxidation in comparison to thermal oxidation In the second part, radical oxidation is investigated for GeO2 growth as an interfacial layer in high-k / Ge gate stack. Using MOSCAP and n-MOSFET devices on Ge, low interface state density combined with drive current and electron mobility enhancement is demonstrated for Ge devices. In the third part, the source/drain junctions for Ge are studied. Ultra-shallow junctions using plasma immersion ion implantation are demonstrated. High n-type dopant activation in Ge using laser annealing is realized along with high performance diodes, significant reduction of contact resistance and integration in a MOSFET process flow.

Download or read book Advanced Gate Stacks for High Mobility Semiconductors written by Athanasios Dimoulas and published by Springer Science & Business Media. This book was released on 2008-01-01 with total page 397 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a comprehensive monograph on gate stacks in semiconductor technology. It covers the major latest developments and basics and will be useful as a reference work for researchers, engineers and graduate students alike. The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any closer to a viable Ge and III-V MOS technology.

Download or read book Graphene Science Handbook written by Mahmood Aliofkhazraei and published by CRC Press. This book was released on 2016-04-27 with total page 719 pages. Available in PDF, EPUB and Kindle. Book excerpt: Discover the Unique Electron Transport Properties of GrapheneThe Graphene Science Handbook is a six-volume set that describes graphene's special structural, electrical, and chemical properties. The book considers how these properties can be used in different applications (including the development of batteries, fuel cells, photovoltaic cells, and s

Download or read book Fabrication of GaAs Devices written by Albert G. Baca and published by IET. This book was released on 2005-09 with total page 372 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides fundamental and practical information on all aspects of GaAs processing and gives pragmatic advice on cleaning and passivation, wet and dry etching and photolithography. Other topics covered include device performance for HBTs (Heterojunction Bipolar Transistors) and FETs (Field Effect Transistors), how these relate to processing choices, and special processing issues such as wet oxidation, which are especially important in optoelectronic devices. This book is suitable for both new and practising engineers.

Download or read book Development of an Innovative Fabrication Method for N MOS to P MOS Tunable Single Metal Gate high kappa Insulator Devices for Multiple Threshold Voltage Applications written by cynthia Faye Burham and published by . This book was released on 2009 with total page 190 pages. Available in PDF, EPUB and Kindle. Book excerpt: Aggressive scaling required to augment device performance has caused conventional electrode materials to approach their physical scaling limits. Alternative metal gate/high dielectric constant (MG/High-[kappa]) stacks have been implemented successfully in commercial devices and hold promise for further scaling based performance advances. Existing MG/High-[kappa] technology does not achieve a single metal n-MOS to p-MOS effective work function (EWF) tuning range suitable for bulk silicon (Si) device applications. Dual metal gates (DMGs) utilizing a separate metal for n-MOS and p-MOS electrodes increases the cost and complexity of fabrication. The research presented herein introduces a method by which the cost and complexity of MG/High-[kappa] device fabrication may be reduced. Innovative fin field effect transistors (FinFETs) incorporating 3 dimensional ultra thin body silicon on oxide (3-D UTB-SOI) technology display superior electrical characteristics compared to bulk Si devices at the nanometer (nm) dimension and require only a +/-200meV n-MOS to p-MOS EWF tuning range around the Si mid-gap. Single metals capable of achieving this +/-200meV EWF tuning range have been evaluated herein and the tuning mechanisms investigated and engineered to develop a single MG/High-[kappa] FinFET the fabrication complexity of which is reduced by 40%. More specifically, the research shows that the metal thickness of titanium nitride/hafnium silicon oxide (TiN/HfSiOx) gate stack may be engineered to achieve an n-MOS (thinner TiN) to p-MOS (thicker TiN) appropriate FinFET EWF tuning range. FinFETs may be fabricated by depositing a single p-MOS appropriate TiN thickness which may be selectively etched back to achieve thinner, n-MOS appropriate films. Similar electrical behavior is exhibited by etched back and as deposited TiN electrode FinFETs. The single metal etch back fabrication method removes many of the additional steps required for DMG fabrication and preserves the integrity of the MG/High-[kappa] interface between n-MOS and p-MOS devices. These advantages result in reduced fabrication complexity and improved reliability and reproducibility.

Download or read book Nanostructured SiGe and Ge for Future Electronic Devices written by Marika Gunji and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: As the packing density of silicon (Si) integrated circuits (IC) increases, scaling requirements are becoming severe. Two approaches are considered to be effective to continue dimensional scaling. One is to alter the active device layer so that it is a semiconductor other than silicon. Silicon-germanium (SiGe) and germanium (Ge) are suitable candidates because of their greater carrier mobilities than Si and their process compatibility with Si substrates. Another approach is to change the device structure or circuit configuration so that there is less power consumption and better performance for higher device packing densities in ICs. Nanoscale structures such as ultra-thin semiconductor-on-insulators or nanowires can be incorporated in future transistors. This dissertation will focus initially on synthesis of highly compressively strained SiGe-on-insulator (SGOI) substrate fabrication. The strain relaxation mechanisms in highly compressively-strained (0.67 % ~ 2.33 % biaxial strain), thin SGOI structures with Ge atomic fraction ranging from 0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were fabricated by selective oxidization of Si from compressively strained SiGe films epitaxially grown on single crystalline Si-on-insulator (SOI) layers. After high temperature oxidation annealing, ~ 30 % of the observed strain relaxation can be attributed to formation of intrinsic SFs and the remaining strain relaxation to stress-driven buckling of the SiGe layers. Second part of the dissertation discusses about the directed synthesis of germanium oxide (GeOx) nanowires (NWs) by locally-catalyzed thermal oxidation of aligned arrays of gold (Au) catalyst-tipped germanium NWs. During oxygen anneals con- ducted above the Au-Ge binary eutectic temperature (T> 361 °C), one-dimensional oxidation of as-grown Ge NWs occurs by diffusion of Ge through the Au-Ge cat- alyst droplet, in the presence of an oxygen containing ambient. Elongated GeOx wires grow from the liquid catalyst tip, consuming the adjoining Ge NW as they grow. The oxide NW diameter is dictated by the catalyst diameter, and their alignment generally parallels that of the growth direction of the initial Ge NWs. Growth rate comparisons reveal a substantial oxidation rate enhancement in the presence of the Au catalyst. Statistical analysis of GeOx nanowire growth by ex situ transmission electron microscopy and scanning electron microscopy suggests a transition from an initial, diameter-dependent kinetic regime, to diameter-independent wire growth. This behavior suggests the existence of an incubation time for GeOx NW nucleation at the start of vapor-liquid-solid oxidation. The dissertation will also discuss the path to obtain higher-k dielectrics on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate capacitance density dielectrics on high-mobility Ge channels, one solution is to interpose a large energy band gap (Eg) insulator with moderate k as an interface layer between a higher-k dielectric and the channel, since higher-k dielectrics tend to have small Eg. Al2O3 layers (k ~ 8) can have stable interfaces with Ge and a large band gap. On the other hand, TiO2 can achieve a much higher k value (~ 60) when in the rutile crystalline phase, but its conduction band offset with Ge is less than 1 eV. TiO2/Al2O3 bilayers deposited on Ge(100) by ALD can achieve low interface trap density with small leakage current after post-metal forming gas anneal. From measurements performed on MOS capacitors, the maximum capacitance at a given frequency increases after the 450 °C forming gas anneal, indicating that the dielectric constant of TiO2 increased to ~ 50 after annealing. Consistent with these results, TEM data indicate that the ALD- grown TiO2 phase had transformed from amorphous phase to the predominant rutile phase after annealing. In order to measure the channel transfer characteristics for this TiO2 (7.5 nm)/Al2O3 (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (Lg = 2 ~ 30 [mu]m) were fabricated. The devices show a subthreshold swing of 110 mV/dec and an on-state current of 73 mA/mm. Measured peak hole mobility reaches 370 cm2/Vs, which suggests the feasibility and potential of TiO2/Al2O3/Ge gate stacks for high performance MOSFETs.

Download or read book Graphene Science Handbook Six Volume Set written by Mahmood Aliofkhazraei and published by CRC Press. This book was released on 2016-04-26 with total page 3379 pages. Available in PDF, EPUB and Kindle. Book excerpt: Graphene is the strongest material ever studied and can be an efficient substitute for silicon. This six-volume handbook focuses on fabrication methods, nanostructure and atomic arrangement, electrical and optical properties, mechanical and chemical properties, size-dependent properties, and applications and industrialization. There is no other major reference work of this scope on the topic of graphene, which is one of the most researched materials of the twenty-first century. The set includes contributions from top researchers in the field and a foreword written by two Nobel laureates in physics. Volumes in the set: K20503 Graphene Science Handbook: Mechanical and Chemical Properties (ISBN: 9781466591233) K20505 Graphene Science Handbook: Fabrication Methods (ISBN: 9781466591271) K20507 Graphene Science Handbook: Electrical and Optical Properties (ISBN: 9781466591318) K20508 Graphene Science Handbook: Applications and Industrialization (ISBN: 9781466591332) K20509 Graphene Science Handbook: Size-Dependent Properties (ISBN: 9781466591356) K20510 Graphene Science Handbook: Nanostructure and Atomic Arrangement (ISBN: 9781466591370)

Download or read book Fabrication and Evaluation of Devices Containing High K Gate Dielectrics and Metal Gate Electrodes for the 70 and 50NM Technology Nodes of ITRS written by and published by . This book was released on 2002 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation has focused on fabrication and characterization of alternative gate stacks consisting of high-K dielectrics and metal gates. This work has presented the evaluation of Ta based metals including Ta, TaNx, and TaSixNy as gate electrodes for their potential use in NMOS devices. For bulk CMOS devices, gate metals must have work functions that are near the conduction and valence band edges of Si. Although several metal gate electrodes have been identified for SiO2 dielectrics based on their work function, thermal stability and carrier concentration, their compatibility with high-K dielectrics is not fully understood. The questions that need to be addressed include thermal stability of metals on high-K, work function values, Fermi level pinning and performance. In this work, we report on the characteristics of metal gate electrodes on SiO2 and HfO2-based dielectrics with respect to equivalent oxide thickness (EOT), flatband voltage (VFB), leakage, work function and thermal stability. The research indicated that the workfunction of TaSixNy is compatible with NMOS devices, provided the right composition is achieved. The improved stability of TaSixNy gates is attributed to the presence of Si and N in the gate electrode, which can improve the film microstructure and the diffusion barrier properties at the gate-dielectric interface. This stability of TaSixNy films may enable high-k dielectrics and metallic electrode to be implemented in advanced CMOS devices. An equivalent oxide thickness of 11.2Å was obtained in TaSixNy /HfO2/p-Si MOS capacitor, while maintaining low leakage current density of 4.1 x 10-2A/cm2 at Vg-VFB=-1V in accumulation. A less EOT increase(~3 Å) was observed with TaSixNy gates compared to other gates (Ta, TaNx, and Ru) due to the excellent oxygen barrier properties of TaSixNy gates, preventing oxygen diffusion into the dielectric through gate electrode and dielectric during annealing. It was observed that trapped charge was incre.

Download or read book High Mobility Germanium MOSFETs written by John Hennessy and published by . This book was released on 2010 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: Germanium offers higher electron and hole mobility than silicon, making it an attractive option for future high-performance MOSFET applications. To date, Ge p-channel device behavior has shown promise, with many reports of measured hole mobilities exceeding that of Si. However, Ge n-channel devices have shown poor performance due to an asymmetric distribution of interface state density (Dit) that degrades electrostatic behavior and carrier mobility. In this work, two methods are investigated for improving the performance of Ge MOSFETs. First, the formation of an interfacial passivation layer via in-situ ozone oxidation is explored. Long channel Ge p- and n-MOSFETs are fabricated with A12 0 3 and HfO2 gate dielectrics deposited by atomic layer deposition (ALD). The ozone surface passivation is observed to result in significant mobility enhancement for all devices, with particularly dramatic improvement in the n-FETs compared to devices with no passivation layer. Measurements of interface state density show a reduction across the entire Ge bandgap. Further improvement of the interface quality has been observed to occur in the presence of n-type channel implants in Ge n-FETs and this effect is studied. All n-type species investigated in this work (P, As, Sb) are seen to result in significant electron mobility enhancement, particularly at low inversion densities. Ge n-FETs receiving channel implants of As or Sb along with the ozone surface passivation exhibit effective electron mobilities higher than Si electron mobility under some conditions of surface electric field for the first time. Substrate bias measurements and low temperature characterization both suggest a reduction in Dit, primarily of acceptor-like trap states near the conduction band.

Download or read book Fabrication and Evaluation of Devices Containing High K Gate Dielectrics and Metal Gate Electrodes for the 70 and 50nm Technology Nodes of ITRS written by YouSeok Suh and published by . This book was released on 2003 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt: Keywords: metal gate, high-k dielectrics, mosfet device.

Download or read book High k Gate Dielectric Materials written by Niladri Pratap Maity and published by CRC Press. This book was released on 2020-12-18 with total page 248 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume explores and addresses the challenges of high-k gate dielectric materials, one of the major concerns in the evolving semiconductor industry and the International Technology Roadmap for Semiconductors (ITRS). The application of high-k gate dielectric materials is a promising strategy that allows further miniaturization of microelectronic components. This book presents a broad review of SiO2 materials, including a brief historical note of Moore’s law, followed by reliability issues of the SiO2 based MOS transistor. It goes on to discuss the transition of gate dielectrics with an EOT ~ 1 nm and a selection of high-k materials. A review of the various deposition techniques of different high-k films is also discussed. High-k dielectrics theories (quantum tunneling effects and interface engineering theory) and applications of different novel MOSFET structures, like tunneling FET, are also covered in this book. The volume also looks at the important issues in the future of CMOS technology and presents an analysis of interface charge densities with the high-k material tantalum pentoxide. The issue of CMOS VLSI technology with the high-k gate dielectric materials is covered as is the advanced MOSFET structure, with its working structure and modeling. This timely volume will prove to be a valuable resource on both the fundamentals and the successful integration of high-k dielectric materials in future IC technology.

Download or read book A Study on Gate Dielectrics for GE Mos Devices written by Chunxia Li and published by Open Dissertation Press. This book was released on 2017-01-28 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation, "A Study on Gate Dielectrics for Ge MOS Devices" by Chunxia, Li, 李春霞, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. DOI: 10.5353/th_b4370387 Subjects: Dielectrics Metal oxide semiconductors, Complementary Germanium

Download or read book Using High K Dielectric Metal Gate with the Chemical Oxide Integration Scheme to Achieve High Performance 20 nm N pMOS Devices written by 陳映璁 and published by . This book was released on 2014 with total page 115 pages. Available in PDF, EPUB and Kindle. Book excerpt: