Download or read book Fabrication and Characterization of Vertical Arrays of Ag Nanowires Grown on Silicon Substrates and Its Application as Electrode Materials in On chip Capacitors for Integrated Circuits written by Ke Xu and published by . This book was released on 2012 with total page 94 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fabrication and Characterization of Vertical Silicon Nanowire Arrays written by Jeffrey M. Weisse and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Thermoelectric devices, which convert temperature gradients into electricity, have the potential to harness waste heat to improve overall energy efficiency. However, current thermoelectric devices are not cost-effective for most applications due to their low efficiencies and high material costs. To improve the overall conversion efficiency, thermoelectric materials should possess material properties that closely resemble a "phonon glass" and an "electron crystal". The desired low thermal and high electrical conductivities allow the thermoelectric device to maintain a high temperature gradient while effectively transporting current. Unfortunately, thermal transport and electrical transport are a closely coupled phenomena and it is difficult to independently engineer each specific conduction mechanism in conventional materials. One strategy to realize this is to generate nanostructured silicon (e.g. silicon nanowires (SiNWs)), which have been shown to reduce thermal conductivity ([kappa]) through enhanced phonon scattering while theoretically preserving the electronic properties; therefore, improving the overall device efficiency. The ability to suppress phonon propagation in nanostructured silicon, which has a bulk phonon mean free path ~ 300 nm at 300 K, has raised substantial interest as an ultra-low [kappa] material capable of reducing the thermal conductivity up to three orders of magnitude lower than that of bulk silicon. While the formation of porous silicon and SiNWs has individually been demonstrated as promising methods to reduce [kappa], there is a lack of research investigating the thermal conductivity in SiNWs containing porosity. We fabricated SiNW arrays using top-down etching methods (deep reactive ion etching and metal-assisted chemical etching) and by tuning the diameter with different patterning methods and tuning the internal porosity with different SiNW etching conditions. The effects of both the porosity and the SiNW dimensions at the array scale are investigated by measuring [kappa] of vertical SiNW arrays using a nanosecond time-domain thermoreflectance technique. In addition to thermoelectric devices, vertical SiNW arrays, due to their anisotropic electronic and optical properties, large surface to volume ratios, resistance to Li-ion pulverization, ability to orthogonalize light absorption and carrier transport directions, and trap light, make vertical SiNW arrays important building blocks for various applications. These may include sensors, solar cells, and Li-ion batteries. Many of these applications benefit from vertical SiNW arrays fabricated on non-silicon based substrates which endow the final devices with the properties of flexibility, transparency, and light-weight while removing any performance limitation of the silicon fabrication substrate. We then developed two vertical transfer printing methods (V-TPMs) that are used to detach SiNW arrays from their original fabrication substrates and subsequently attach them to any desired substrate while retaining their vertical alignment over a large area. The transfer of vertically aligned arrays of uniform length SiNWs is desirable to remove the electrical, thermal, optical, and structural impact from the fabrication substrate and also to enable the integration of vertical SiNWs directly into flexible and conductive substrates. Moreover, realization of a thermoelectric device requires the formation of electrical contacts on both sides of the SiNW arrays. We formed metallic contacts on both ends of the SiNW arrays with a mechanical supporting and electrical insulating polymer in between. Electrical characterization of the SiNW devices exhibited good current-voltage (I-V) characteristics independent of substrates materials and bending conditions. We believe the V-TPMs developed in this work have great potential for manufacturing practical thermoelectric devices as well as high performing, scalable SiNW array devices on flexible and conducting substrates.

Download or read book Silicon and Silicon Carbide Nanowires written by John Paul Alper and published by . This book was released on 2014 with total page 94 pages. Available in PDF, EPUB and Kindle. Book excerpt: For applications in mobile and remote sensing platforms, microsupercapacitors are attractive energy storage devices due to their robust lifetimes and high specific power capacity. Utilization of green electrolytes in these devices reduces environmental impact and simplifies packaging by avoiding the stringent oxygen and moisture free conditions required for organic and ionic liquid based electrolytes. Porous silicon nanowire based microsupercapacitor electrode materials are promising for on chip applications using an environmentally benign aqueous electrolyte, 1 M KCl, however they are prone to oxidation. A silicon carbide coating was found to mitigate this issue. The fabrication techniques, involving low-temperature electroless etching of silicon, are compatible with current integrated circuit processing methods and may be readily integrated at the micro device level. The electrode materials are in good electrical contact with the underlying substrate and require no additional current collector. The base porous silicon nanowires are coated with a thin silicon carbide passivation layer by low pressure chemical vapor deposition. The demonstrated capacitance of the electrode materials, ~1700 [mu]F/cm2 projected area, is comparable to other carbon based microsupercapacitor electrodes, remains stable over many charge/discharge cycles, and maintains capacitive behavior over a wide range of charge/discharge rates. An improved passivation method for the porous silicon nanowires has also been developed. The selective coating procedure deposits an ultra-thin (~ 1-3 nm) carbon sheath over the nanowires and passivates them. The ultra-thin nature of the coating enables solvent access to the pore area and hence a large improvement of active specific surface over the SiC coated PSiNWs discussed above. The electrochemical performance of these coated nanowires is characterized in both an aqueous electrolyte and an ionic liquid electrolyte. Specific capacitance values reaching 325 mF cm 2 are achieved in ionic liquid, and calculations indicate that the theoretical maximum capacitance of the pristine wires is reached. TEM studies confirm the coating thickness and its conformality. Raman spectroscopy indicates that the carbon in the coating is mainly sp2 hybridized, with corresponding high conductivity. At the time of writing, these materials represent the largest specific energy microsupercapacitor electrode published. A test device is prepared and demonstrated powering an LED. The testing results of silicon carbide (SiC) nanowires (NW) as an electrode material for micro-supercapacitors is described. SiC NWs are grown on a SiC thin film coated with a thin Ni catalyst layer via chemical vapor deposition. A specific capacitance of ~240 μF cm-2 is demonstrated. Charge-discharge studies demonstrate the SiC nanowires exhibit exceptional stability, with 95% capacitance retention after 2×105 charge/discharge cycles in an environmentally benign, aqueous electrolyte. Doping of the nanowires with nitrogen through the addition of 5 at% ammonia to the precursor gas flow rate improves the conductivity of the nanowire films by over an order of magnitude leading to increased power capabilities. A method to transfer silicon and silicon carbide nanowire arrays to arbitrary substrates while maintaining electrical contact through the entire array is elucidated. The nanowires are grown on graphene sheets on SiO2 coupons. The graphene acts as both the flexible material for maintaining structural continuity and electrical contact through the array during transfer. The SiO2 acts as the sacrificial growth substrate which is etched after growth in order to release the nanowire/graphene hybrid. The nanowire/graphene hybrids are structurally characterized by XRD and electron microscopy. Good electrical contact is confirmed through testing of the SiCNW/graphene hybrids as supercapacitor electrode materials in an aqueous electrolyte. The specific capacitance, ~340 mF cm-2, is similar to SiCNW arrays grown on oxide while the electrical conductivity is improved and cycling stability tests show less than a 1% decrease in capacitance after 10,000 cycles.

Download or read book Chemical Abstracts written by and published by . This book was released on 2002 with total page 2540 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Fabrication and Characterization of Vertically Aligned Carbon Nanofibers VACNF as Amperometric Biosensors on a Silicon compatible Platform written by Kimberly Caitlin MacArthur and published by . This book was released on 2012 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis presents fabrication, characterization and initial results of vertically aligned carbon nanofibers (VACNF)-based electrodes for use as electrochemical sensors. VACNFs are nanostructures that can be fabricated to the desired specifications using a plasma-enhanced chemical-vapor deposition process and are ideal candidates for electrode material because of their excellent electrical and structural properties. The first step of the fabrication of VACNFs on silicon substrates involved photolithography to pattern the interconnects and the catalysts (nickel dots). VACNFs were then grown on silicon substrates from the nickel catalysts, whose size determines the growth of a single nanofiber or a forest of nanofibers. This work presents a method for growth of nanofiber forest for redundancy and uniform vertical growth. A reservoir was built around the nanofibers to keep the liquid samples in contact with the nanofibers during testing. Nanofiber electrodes were characterized electrochemically using ruthenium hexamine trichloride to ensure proper functionality. The biosensor is customizable to selectively detect various elements or compounds depending on the binding materials used on the nanofibers. One example of a sample that can be detected with VACNF electrodes is glucose. The enzymes, horseradish peroxidase and glucose oxidase, were applied to the nanofibers and were immobilized for the testing of glucose. The reference electrode of the electrochemical analyzer was inserted into the reservoir containing the glucose and multiple analyses were performed. The nanofiber electrodes were able to collect the electrons from the electrochemical reactions of glucose and the enzymes. Amperometric data was gathered for the oxidation and reduction potentials and the current was measured as a function of the glucose concentration. Vertically aligned carbon nanofibers fabricated on silicon substrates are ideal electrodes for integration with silicon compatible structures such as complementary metal-oxide-semiconductor (CMOS) microelectronics based transmitting and signal processing integrated circuits.

Download or read book Copye van het vonnis uytgesproken by Schepenen van der Keure der stad Gend tot laste van Jacobus Janssens ge xecuteert den 17 July 1790 written by and published by . This book was released on 1790 with total page 210 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Synthesis Characterization and Integration of Silicon Nanowires for Nanosystems Technology written by Gregory Stephen Doerk and published by . This book was released on 2010 with total page 256 pages. Available in PDF, EPUB and Kindle. Book excerpt: Silicon's chemical stability, high natural abundance (as the second most common element in the earth's crust), mechanical stiffness, and semiconducting behavior have made it the subject of extensive scientific investigation and the material of choice for both the microelectronics and microelectromechanical device industries. The success of Moore's Law that demands continual size reduction has directed it to a central place in emerging nanoscience and nanotechnology as well. Crystalline nanowires (NWs) are one nanostructured form that silicon may take that has sparked significant interest as they can exhibit considerable confinement effects and high surface-to-volume ratios, but may be interfaced simply along one direction for the determination of material properties and implementation into new technologies. The expense and difficulty involved in the creation of semiconductor nanowires using the "top down" fabrication techniques of the microelectronics industry has promoted an explosion of chemical synthetic "bottom up" techniques to produce high quality crystalline nanowires in large quanitities. Nevertheless, bottom up synthesized Si NWs retain a new set of challenges for their successful integration into reliable, high-performance devices, which is hindered by an incomplete understanding of the factors controlling their material properties. The first chapter of this dissertation introduces the motivation for studying semiconductor NWs and the benefits of limiting the scope to silicon alone. A brief survey of the current understanding of thermal conductivity in silicon nanowires provides prime examples of how confinement effects and surface morphology may dramatically alter nanowire properties from their bulk crystal counterparts. The particular challenges to bottom up silicon nanowire device integration and characterization are noted, especially related to Si nanowires that are grown epitaxially on crystal silicon substrates, and Raman spectroscopy is introduced as a promising optical characterization and metrology tool for semiconductor nanowire based devices. Chapter two describes the vapor-liquid-solid (VLS) mechanism for the synthesis of very high quality, single-crystal silicon nanowires using Au and Pt catalyst nanoparticles. A new technique is presented for the simplified synthesis of branched silicon nanowires based on the migration of Au catalyst during an hydrogen anneal intermediate between growth stages, and the faceting behavior at synthetic stages is revealed by the analysis of electron microscope images. Synthesis of solid and porous Si nanowires based on Ag mediated electrochemical silicon etching is described as well. The third chapter specifies new processing techniques developed with future device integration of epitaxially VLS-grown Si nanowires in mind. Epitaxially bridging nanowires are shown to provide an excellent platform for single-wire electrical and mechanical property measurements. Galvanic displacement through block copolymer micelle/homopolymer surface templates is demonstrated as a means to deposit catalyst nanoparticles with controlled sizes and areal densities in a variety of geometries and with registration to photolithographic patterns. Ex situ boron doping by the direct hydrogen reduction of boron tribromide is shown to achieve active concentrations exceeding 1019 cm-3 with high axial uniformity, while avoiding the adverse impact on nanowire morphology that is often observed with in situ boron doping of silicon nanowires. Chapter four describes the characteristics of Raman spectroscopy that are relevant to studying individual semiconductor nanowires. Careful spectral measurements show that the anharmonic dependence of Raman spectra on temperature for individual Si nanowires remains unchanged from the bulk crystal for diameters down to 30 nm, regardless of surface morphology. Using this result, a new technique for measuring the thermal conductivity of individual semiconductor nanowires is then outlined based on Raman thermal mapping of individual cantilevered nanowires. Finally, the dissertation is concluded with suggestions for possible future experiments. One avenue is to probe more deeply the morphology of faceted silicon nanowires and nanotrees and its impact on their transport physics. Another possible route for further study would be to explore new characterization and metrological applications of Raman spectrocopy for semiconductor nanowires.

Download or read book Fabrication of High Aspect Ratio Silicon Nanostructure Arrays by Metal assisted Etching written by Shih-wei Chang (Ph.D.) and published by . This book was released on 2010 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt: The goal of this research was to explore and understand the mechanisms involved in the fabrication of silicon nanostructures using metal-assisted etching. We developed a method utilizing metal-assisted etching in conjunction with block copolymer lithography to create ordered and densely-packed arrays of high-aspect-ratio single-crystal silicon nanowires with uniform crystallographic orientations. Nanowires with sub-20 nm diameters were created as either continuous carpets or as carpets within trenches. Wires with aspect ratios up to 220 with much reduced capillary-induced clustering were achieved through post-etching critical point drying. The size distribution of the diameters was narrow and closely followed the size distribution of the block copolymer. Fabrication of wires in topographic features demonstrated the ability to accurately control wire placement. The flexibility of this method will facilitate the use of such wire arrays in micro- and nano-systems in which high device densities and/or high surface areas are desired. In addition, we report a systematic study of metal-catalyzed etching of (100), (110), and (111) silicon substrates using gold catalysts with varying geometrical characteristics. It is shown that for isolated catalyst nanoparticles and metal meshes with small hole spacings, etching proceeded preferentially in the 100 direction. However, etching was confined in the direction vertical to the substrate surface when a catalyst mesh with large hole spacings was used. This result was used to demonstrate the use of metal-assisted etching to create arrays of vertically-aligned polycrystalline and amorphous silicon nanowires etched from deposited silicon thin films using catalyst meshes with relatively large hole spacings. The ability to pattern wires from polycrystalline and amorphous silicon thin films opens the possibility of making silicon nanowire-array-based devices on a much wider range of substrates. Finally, we demonstrated the fabrication of a silicon-nanopillar-based nanocapacitor array using metal-assisted etching and electrodeposition. The capacitance density was increased significantly as a result of an increased electrode area made possible by the catalytic etching approach. We also showed that the measured capacitance densities closely follow the expected trend as a function of pillar height and array period. The capacitance densities can be further enhanced by increasing the array density and wire length with the incorporation of known self-assembly-based patterning techniques such as block copolymer lithography.

Download or read book Fabrication and Characterization of Silicon Nanowires written by Vikram Passi and published by LAP Lambert Academic Publishing. This book was released on 2012-07 with total page 124 pages. Available in PDF, EPUB and Kindle. Book excerpt: When dimensions of material approach nanoscale, they often reveal startling properties. These unique properties when compared to bulk material make them interesting candidates for new technologies. In a race to sustain Moore's Law, silicon nanowires which possess remarkable properties diverse from bulk-silicon have gained notable attention. With advancement in technology engineers have mastered the art of fabrication of nanowires, but there exists a big gap in understanding various phenomena at this scale. The aim of this work is to bridge the gap and give an insight into some interesting properties and application of silicon nanowires. Using top-down lithography Silicon nanowires are fabricated and various mechanical and electrical properties are studied. The use of functionalized silicon nanowires for gas detection is demonstrated with very large sensitivity and detection window reported for the first time.

Download or read book Fabrication of Silicon Nanowires with Controlled Nano scale Shapes Using Wet Anisotropic Etching written by Bailey Anderson Yin and published by . This book was released on 2015 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt: Silicon nanowires can enable important applications in energy and healthcare such as biochemical sensors, thermoelectric devices, and ultra-capacitors. In the energy sector, for example, as the need for more efficient energy storage continues to grow for enabling applications such as electric vehicles, high energy storage density capacitors are being explored as a potential replacement to traditional batteries that lack fast charge/discharge rates as well as have shorter life cycles. Silicon nanowire based ultra-capacitors offer increased energy storage density by increasing the surface area per unit projected area of the electrode, thereby allowing more surface “charge” to reside. The motivation behind this dissertation is the study of low-cost techniques for fabrication of high aspect ratio silicon nanowires with controlled geometry with an exemplar application in ultra-capacitors. Controlled transfer of high aspect ratio, nano-scale features into functional device layers requires anisotropic etch techniques. Dry reactive ion etch techniques are commonly used since most solution-based wet etch processes lack anisotropic pattern transfer capability. However, in silicon, anisotropic wet etch processes are available for the fabrication of nano-scale features, but have some constraints in the range of geometry of patterns that they can address. While this lack of geometric and material versatility precludes the use of these processes in applications like integrated circuits, they can be potentially realized for fabricating nanoscale pillars. This dissertation explores the geometric limitations of such inexpensive wet anisotropic etching processes and develops additional methods and geometries for fabrication of controlled nano-scale, high aspect ratio features. Jet and Flash Imprint Lithography (J-FILTM) has been used as the preferred pre-etch patterning process as it enables patterning of sub-50 nm high density features with versatile geometries over large areas. Exemplary anisotropic wet etch processes studied include Crystalline Orientation Dependent Etch (CODE) using potassium hydroxide (KOH) etching of silicon and Metal Assisted Chemical Etching (MACE) using gold as a catalyst to etch silicon. Experiments with CODE indicate that the geometric limitations of the etch process prevent the fabrication of high aspect ratio nanowires without adding a prohibitive number of steps to protect the pillar geometry. On the other hand, MACE offers a relatively simple process for fabricating high aspect ratio pillars with unique cross sections, and has thus been pursued to fabricate fully functional electrostatic capacitors featuring both circular and diamond-shaped nano-pillar electrodes. The capacitance of the diamond-shaped nano-pillar capacitor has been shown to be ~77.9% larger than that of the circular cross section due to the increase in surface area per unit projected area. This increase in capacitance approximately matches the increase calculated using analytical models. Thus, this dissertation provides a framework for the ability to create unique sharp cornered nanowires that can be explored further for a wider variety of cross sections.

Download or read book Controlled Growth and Orientation in Aluminum mediated Crystallization of Silicon Nanowires and Thin Films written by Mel Hainey and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Metal-mediated silicon crystallization has received extensive study as a means to form silicon wires and thin films for electronic and photovoltaic applications. Typical metals used in these processes, such as gold, silver, nickel, and copper, are expensive and act as deep-level traps in silicon, making incorporation into the final silicon crystal undesirable. In contrast, aluminum is earth-abundant and acts as a p-type dopant in silicon, and the low Al-Si eutectic temperature (577C) enables silicon crystallization under conditions compatible with a wide variety of substrates.In this thesis, aluminum-mediated silicon nanowire and thin film growth is investigated, and the effects of growth parameters such as temperature, pressure, and substrate surface energy on nanowire orientation and morphology and thin film morphology are investigated. In particular, through controlled growth temperature, reactor pressure, and silane partial pressure, growth on aluminum-catalyzed silicon nanowires in high energy growth directions such as 110 and 100 can be realized. Wires grown in high-energy growth directions have unique morphologies that suggest a different growth mechanism than the standard vapor-liquid-solid nanowire growth mechanism. Because these wires are grown in a region with partially depleted silane concentrations, this regime is described as silane-depleted vapor-liquid-solid growth. Along with promoting growth in high energy growth directions, reactor temperature and pressure can be used to change the shape of 111 wires to pyramids. These pyramids have improved anti-reflective properties compared to vertical nanowire arrays, enabling black silicon textures to be grown on silicon substrates. Because the wires and pyramids are p-type, growth on n-type substrates enables black silicon solar cells to be fabricated in a process that combines texturing and junction formation into a single step.Aluminum-induced crystallization of silicon thin films offers a unique method for producing highly (111) oriented polycrystalline thin films on amorphous substrates. Al and a-Si are deposited on glass or other substrates, and then annealed below the Al-Si eutectic temperature. For film thicknesses below 50nm, the a-Si diffuses through the Al film and nucleates at the Al/substrate interface. By using plasma surface treatments to change the surface energies of the fused quartz substrates, silicon crystallization rates and grain sizes can be manipulated. Furthermore, by combining multiple surface treatments on a single substrate, preferential crystallization at the low-energy interface can be realized, allowing for the formation of patterned AIC-films from uniform, continuous initial a-Si and Al layers.Finally, along with pattern formation, these AIC-Si films are able to act as seed layers for III-nitride semiconductor growth on fused quartz and other substrates. Through use of an AlN buffer layer, highly c-axis oriented GaN films can be grown using metalorganic chemical vapor deposition on AIC-Si substrates. Post growth characterization indicates that the GaN films follow the template provided by the AIC-Si films, with uniform surface normal orientation and random in-plane orientation. Defect analysis suggests that threading dislocation densities within grains are comparable to GaN grown on bulk Si (111) substrates. Additional studies have extended the GaN on AIC-Si process to other substrates, including oxidized Si (001) and polycrystalline diamond, with GaN films showing similar morphologies to those grown on AIC-Si on fused quartz.Overall, this thesis demonstrates how aluminum-mediated crystallization of silicon can be used to fabricate thin films and nanowires with a variety of orientations and morphologies. Furthermore, the initial demonstration of these wires and thin films in photovoltaic and electronic applications is also presented. Ultimately, aluminum-mediated silicon crystallization is demonstrated to be a flexible, controllable approach for producing a variety of technologically relevant nanowires and thin films.

Download or read book Fabrication of Vertical Silicon Nanowires Through Metal Assisted Deposition written by Matthew Garett Young and published by . This book was released on 2012 with total page 232 pages. Available in PDF, EPUB and Kindle. Book excerpt: Controlled and ordered growth of Si nanowires through a low temperature fabrication method compatible with CMOS processing lines is a highly desirable replacement to future electronic fabrication technologies as well as a candidate for a low cost route to inexpensive photovoltaics. This stems from the fact that traditional CMOS based electronics are hitting physical barriers that are slowing the Moore's Law trend as well as the demand for an inexpensive solar cell technology that can obtain grid parity. A fractional factorial growth study is presented that compares the growth of Au and Al catalyzed Si nanowires at temperatures ranging from 150 to 400° C. Dense and prolific growth of Si nanowires on 111 and 100 Si substrates as well as glass substrates was obtained using a Au catalyst at temperatures of 400° C. An overview is given that considers all growth experiments and includes TEM analysis of individual Si nanowires grown on Si substrates showing nanowires to be both crystalline and amorphous in nature. Optical transmission data of bulk Si nanowire films on glass substrates showed that the collective optical properties were highly desirable as transmission was minimized over the 300 to 1400 nm wavelength range at different transmission angles. Collectively, a growth platform is presented from which further material study will yield advanced Si nanowire based devices, satisfying a demand by the ITRS and the scientific community at large for electronics that can continue the Moore's law trend and inexpensive photovoltaics capable of meeting the consumer demand for grid parity.

Download or read book Nanowire Field Effect Transistors Principles and Applications written by Dae Mann Kim and published by Springer Science & Business Media. This book was released on 2013-10-23 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: “Nanowire Field Effect Transistor: Basic Principles and Applications” places an emphasis on the application aspects of nanowire field effect transistors (NWFET). Device physics and electronics are discussed in a compact manner, together with the p-n junction diode and MOSFET, the former as an essential element in NWFET and the latter as a general background of the FET. During this discussion, the photo-diode, solar cell, LED, LD, DRAM, flash EEPROM and sensors are highlighted to pave the way for similar applications of NWFET. Modeling is discussed in close analogy and comparison with MOSFETs. Contributors focus on processing, electrostatic discharge (ESD) and application of NWFET. This includes coverage of solar and memory cells, biological and chemical sensors, displays and atomic scale light emitting diodes. Appropriate for scientists and engineers interested in acquiring a working knowledge of NWFET as well as graduate students specializing in this subject.

Download or read book Semiconductor Nanowires written by J Arbiol and published by Elsevier. This book was released on 2015-03-31 with total page 573 pages. Available in PDF, EPUB and Kindle. Book excerpt: Semiconductor nanowires promise to provide the building blocks for a new generation of nanoscale electronic and optoelectronic devices. Semiconductor Nanowires: Materials, Synthesis, Characterization and Applications covers advanced materials for nanowires, the growth and synthesis of semiconductor nanowires—including methods such as solution growth, MOVPE, MBE, and self-organization. Characterizing the properties of semiconductor nanowires is covered in chapters describing studies using TEM, SPM, and Raman scattering. Applications of semiconductor nanowires are discussed in chapters focusing on solar cells, battery electrodes, sensors, optoelectronics and biology. - Explores a selection of advanced materials for semiconductor nanowires - Outlines key techniques for the property assessment and characterization of semiconductor nanowires - Covers a broad range of applications across a number of fields

Download or read book High Throughput Manufacturing of Silicon Nanobridges for the Fabrication of 3D Gate all around Field Effect Transistors written by Jin Yong Oh and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Self-assembled nanowires chemically synthesized by bottom-up approaches have attracted considerable attention due to their properties that are not common in their bulk or thin film counterparts. Their potential to offer novel functionality opens up opportunities for innovative genres of devices. Indeed, a number of innovative devices, such as transistors, diodes, bio/chemical sensors, photovoltaic devices, and even embryonic low-density integrated circuits, have been demonstrated by using various kinds of nanowires. In contrast to nanostructured materials created by the microfabrication technology pursued by the microelectronics industry, self-assembled nanowires inheritedly exhibit a high degree of variability in their dimensions, densities, locations, and alignment, etc. Despite the promise of nanowires, such uncertainty prevents them from utilization in mass-manufacturing processes and large-scale device integration. This dissertation aimed to devise a viable and high-throughput growth-in-place technique for creating well-ordered nanowire arrays without costly and tedious post-growth processing. This dissertation also intended to demonstrate novel devices using the nanobridges created by the growth-in-place technique and nanowire ensembles. In the first section of the dissertation, a couple of popular modalities for creating nanowire devices, including growth-in-place techniques, were briefly reviewed to improve our understanding of their various aspects. Among multiple bottom-up growth techniques, a revised nanobridging technique with new process recipes for depositing catalytic gold nanoparticles was explored to enhance its repeatability and throughput. Yields of the nanobridges were improved with the new schemes such as adding HF acid to nanoparticle colloid and employing a surface linker treatment on the substrate for catalyst deposition while maintaining deposition selectivity. This dissertation demonstrated that Si nanobridges could become building blocks of 3D gate-all-around FETs, charge-trap nonvolatile memory devices, and photosensitive transistors. Here, high yields of the nanobridges with improved arrangement allowed integration of multiple devices per batch. The nanobridge FETs showed successful switching characteristics, and the nanobridge memory devices showed low voltage programming/erasing operations due to the enhanced electric fields exerted by the surround gate. High photosensitivity of the off currents of the nanobridge MOSFET offered an opportunity to create novel electro-optical switching devices. Although these bridge devices exhibited proof-of-concept level performance and needed far more optimization for attaining competitive performance, they showed the feasibility of expanding the realm of nanobridge applications. Other than exploring the bottom-up approach of synthesizing nanowires right onto the electrodes in a well-organized fashion, the dissertation looked into protocols for maneuvering 1D nanostructure ensembles and manufacturing devices thereof. Exploiting nanowire ensemble en masse is attractive because this approach allows substrate recycling and simple device fabrication. One example of nanowire ensemble devices was capacitive chemical sensors, which had nanowire ensembles in the active sensing regions. These sensors showed pH sensitivities as high as the theoretical limit owing to their surface areas and high-density surface sites. Another example was flexible 2D devices created by transferring and then interfacing 1D structures with elastomer (polyurethane) films. Here, the mechanism of harvesting 1D structures was discussed with the help of simulation-based analysis, and electrical interfacing of the transferred structures was presented for creating flexible devices. In the last part of this dissertation, the nanobridging technique was evaluated from the practical point of view, and its perspectives were discussed thoroughly. The presented nanobridging technique seems to be uncompetitive compared to the matured and state-of-the-art modern microfabrication technology. However, the work carried out in this dissertation indicates that the bridging technique can help integrating heteroepitaxial nanowires on the Si platform. In particular, catalyst-free heteroepitaxial growth of nanowires on Si substrates can help the continuation of the microelectronics paradigm, 'Saller and Faster,' typically represented by 'Moore's Law.'

Download or read book Vertically Stacked Silicon Nanowire written by and published by . This book was released on with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Xii, 63 leaves : ill. ; 30 cm.

Download or read book Fabrication and Electrical Characterization of Silicon Nanowire Arrays written by Sarah M. Dilts and published by . This book was released on 2004 with total page 100 pages. Available in PDF, EPUB and Kindle. Book excerpt: