Download or read book Energy Efficient Microarchitectures for On chip Voltage Regulation and Low Noise Computing written by Yuxin Bai and published by . This book was released on 2016 with total page 128 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Power- and energy-efficiency are significant requirements in virtually all computer systems, from mobile devices to large-scale data centers. Power delivery is a process that distributes stable supply voltages to gates within an integrated circuit (IC). The design of such a delivery network is a critical task to guarantee functionality, timing, and operation reliability, and significantly affects the power- and energy-efficiency of a high performance IC. Therefore, microarchitectural solutions that are aware of the power delivery system, should be capable of exploring a larger optimization space for energy efficient computer systems. This thesis proposes two microarchitectural techniques that leverage the design tradeoffs of the underlying power delivery networks to achieve energy-efficient computing. First, the use of MOS current-mode logic (MCML) is explored as a fast and low-noise alternative to static CMOS logic in microprocessors, thereby improving the performance, energy-efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10 × -100× smaller than the noise generated by a static CMOS circuit, and therefore can significantly relax the typical design constraints imposed on the power delivery network. Unlike a static CMOS circuit, in which dynamic power is proportional to the clock frequency, an MCML circuit dissipates a constant power independent of the clock frequency. Although these traits make MCML highly energy-efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at a modest clock rate and with a low activity factor. To address this challenge, this thesis explores a single-core microarchitecture for MCML that takes advantage of the C-slow retiming technique, and runs at a high frequency with low complexity to save energy. This design principle differs fundamentally from the contemporary multicore design paradigm for static CMOS, which relies on a large number of gates running in parallel at modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates at a level of performance within 13% of a conventional, eight-core static CMOS system, while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of the MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length. Dynamic voltage and frequency scaling (DVFS) is an effective technique used in power management. Voltage regulators are key components for power generation during the power delivery process. Emerging on-chip voltage regulators has the potential to increase the energy efficiency of computer systems by enabling the control of DVFS at a fine granularity in both space and time. A low dropout voltage regulator (LDO) is suitable for on-chip integration due to its speed, regulation quality, and area advantages. The energy conversion efficiency of an LDO, however, is dependent on the ratio of the input and output voltages, which results in energy waste when DVFS is applied over a wide voltage range. A DVFS framework that relies on a hierarchy of off-chip switching regulators and per-core on-chip LDOs is proposed. It ensures fast DVFS in nanoseconds and a more than 90% regulator efficiency over a wide voltage range. A control policy using a reinforcement learning (RL) approach is proposed to exploit the fine-granularity control of power and the high regulator efficiency enabled by the framework. Per-core RL agents learn and improve their DVFS policies independently, while retaining the ability to coordinate their actions to accomplish system level power management objectives. The proposed framework achieves 18% greater energy efficiency than a typical per-core DVFS framework using on-chip switching regulators when evaluated on a mix of 14 parallel and 13 multiprogrammed workloads. Moreover, the proposed RL policy is 21% more energy efficient as compared to an oracle policy with coarse-grained DVFS"--Pages vi-vii.

Download or read book Low Power Circuits for Emerging Applications in Communications Computing and Sensing written by Fei Yuan and published by CRC Press. This book was released on 2018-12-07 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book addresses the need to investigate new approaches to lower energy requirement in multiple application areas and serves as a guide into emerging circuit technologies. It explores revolutionary device concepts, sensors, and associated circuits and architectures that will greatly extend the practical engineering limits of energy-efficient computation. The book responds to the need to develop disruptive new system architecutres, circuit microarchitectures, and attendant device and interconnect technology aimed at achieving the highest level of computational energy efficiency for general purpose computing systems. Features Discusses unique technologies and material only available in specialized journal and conferences Covers emerging applications areas, such as ultra low power communications, emerging bio-electronics, and operation in extreme environments Explores broad circuit operation, ex. analog, RF, memory, and digital circuits Contains practical applications in the engineering field, as well as graduate studies Written by international experts from both academia and industry

Download or read book E3 written by Madhu Sarava Govindan and published by . This book was released on 2010 with total page 436 pages. Available in PDF, EPUB and Kindle. Book excerpt: Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry. Power dissipation, increasing wire delays, and increasing design complexity have forced industry to embrace multi-core architectures or chip multiprocessors (CMPs). While CMPs mitigate wire delays and design complexity, they do not directly address single-threaded performance. Additionally, programs must be parallelized, either manually or automatically, to fully exploit the performance of CMPs. Researchers have recently proposed an architecture called Explicit Data Graph Execution (EDGE) as an alternative to conventional CMPs. EDGE architectures are designed to be technology-scalable and to provide good single-threaded performance as well as exploit other types of parallelism including data-level and thread-level parallelism. In this dissertation, we examine the energy efficiency of a specific EDGE architecture called TRIPS Instruction Set Architecture (ISA) and two microarchitectures called TRIPS and TFlex that implement the TRIPS ISA. TRIPS microarchitecture is a first-generation design that proves the feasibility of the TRIPS ISA and distributed tiled microarchitectures. The second-generation TFlex microarchitecture addresses key inefficiencies of the TRIPS microarchitecture by matching the resource needs of applications to a composable hardware substrate. First, we perform a thorough power analysis of the TRIPS microarchitecture. We describe how we develop architectural power models for TRIPS. We then improve power-modeling accuracy using hardware power measurements on the TRIPS prototype combined with detailed Register Transfer Level (RTL) power models from the TRIPS design. Using these refined architectural power models and normalized power modeling methodologies, we perform a detailed performance and power comparison of the TRIPS microarchitecture with two different processors: 1) a low-end processor designed for power efficiency (ARM/XScale) and 2) a high-end superscalar processor designed for high performance (a variant of Power4). This detailed power analysis provides key insights into the advantages and disadvantages of the TRIPS ISA and microarchitecture compared to processors on either end of the performance-power spectrum. Our results indicate that the TRIPS microarchitecture achieves 11.7 times better energy efficiency compared to ARM, and approximately 12% better energy efficiency than Power4, in terms of the Energy-Delay-Squared (ED2) metric. Second, we evaluate the energy efficiency of the TFlex microarchitecture in comparison to TRIPS, ARM, and Power4. TFlex belongs to a class of microarchitectures called Composable Lightweight Processors (CLPs). CLPs are distributed microarchitectures designed with simple cores and are highly configurable at runtime to adapt to resource needs of applications. We develop power models for the TFlex microarchitecture based on the validated TRIPS power models. Our quantitative results indicate that by better matching execution resources to the needs of applications, the composable TFlex system can operate in both regimes of low power (similar to ARM) and high performance (similar to Power4). We also show that the composability feature of TFlex achieves a signification improvement (2 times) in the ED2 metric compared to TRIPS. Third, using TFlex as our experimental platform, we examine the efficacy of processor composability as a potential performance-power trade-off mechanism. Most modern processors support a form of dynamic voltage and frequency scaling (DVFS) as a performance-power trade-off mechanism. Since the rate of voltage scaling has slowed significantly in recent process technologies, processor designers are in dire need of alternatives to DVFS. In this dissertation, we explore processor composability as an architectural alternative to DVFS. Through experimental results we show that processor composability achieves almost as good performance-power trade-offs as pure frequency scaling (no changes in supply voltages), and a much better performance-power trade-off compared to voltage and frequency scaling (both supply voltage and frequency change). Next, we explore the effects of additional performance-improving techniques for the TFlex system on its energy efficiency. Researchers have proposed a variety of techniques for improving the performance of the TFlex system. These include: (1) block mapping techniques to trade off intra-block concurrency with communication across the operand network; (2) predicate prediction and (3) operand multi-cast/broadcast mechanism. We examine each of these mechanisms in terms of its effect on the energy efficiency of TFlex, and our experimental results demonstrate the effects of operand communication, and speculation on the energy efficiency of TFlex. Finally, this dissertation evaluates a set of fine-grained power management (FGPM) policies for TFlex: instruction criticality and controlled speculation. These policies rely on a temporally and spatially fine-grained dynamic voltage and frequency scaling (DVFS) mechanism for improving power efficiency. The instruction criticality policy seeks to improve power efficiency by mapping critical computation in a program to higher performance-power levels, and by mapping non-critical computation to lower performance-power levels. Controlled speculation policy, on the other hand, maps blocks that are highly likely to be on correct execution path in a program to higher performance levels, and the other blocks to lower performance levels. Our experimental results indicate that idealized instruction criticality and controlled speculation policies improve the operating range and flexibility of the TFlex system. However, when the actual overheads of fine-grained DVFS, especially energy conversion losses of voltage regulator modules (VRMs), are considered the power efficiency advantages of these idealized policies quickly diminish. Our results also indicate that the current conversion efficiencies of on-chip VRMs need to improve to as high as 95% for the realistic policies to be feasible.

Download or read book Energy Efficient High Performance Processors written by Jawad Haj-Yahya and published by Springer. This book was released on 2018-03-22 with total page 176 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

Download or read book Energy Efficient Fault Tolerant Systems written by Jimson Mathew and published by Springer Science & Business Media. This book was released on 2013-09-07 with total page 347 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes the state-of-the-art in energy efficient, fault-tolerant embedded systems. It covers the entire product lifecycle of electronic systems design, analysis and testing and includes discussion of both circuit and system-level approaches. Readers will be enabled to meet the conflicting design objectives of energy efficiency and fault-tolerance for reliability, given the up-to-date techniques presented.

Download or read book Power Efficient Computer Architectures written by Magnus Själander and published by Springer Nature. This book was released on 2022-05-31 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt: As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture. Table of Contents: Introduction / Voltage and Frequency Management / Heterogeneity and Specialization / Communication and Memory Systems / Conclusions / Bibliography / Authors' Biographies

Download or read book Nanomagnetic and Spintronic Devices for Energy Efficient Memory and Computing written by Jayasimha Atulasimha and published by John Wiley & Sons. This book was released on 2016-01-27 with total page 352 pages. Available in PDF, EPUB and Kindle. Book excerpt: Nanomagnetic and spintronic computing devices are strong contenders for future replacements of CMOS. This is an important and rapidly evolving area with the semiconductor industry investing significantly in the study of nanomagnetic phenomena and in developing strategies to pinpoint and regulate nanomagnetic reliably with a high degree of energy efficiency. This timely book explores the recent and on-going research into nanomagnetic-based technology. Key features: Detailed background material and comprehensive descriptions of the current state-of-the-art research on each topic. Focuses on direct applications to devices that have potential to replace CMOS devices for computing applications such as memory, logic and higher order information processing. Discusses spin-based devices where the spin degree of freedom of charge carriers are exploited for device operation and ultimately information processing. Describes magnet switching methodologies to minimize energy dissipation. Comprehensive bibliographies included for each chapter enabling readers to conduct further research in this field. Written by internationally recognized experts, this book provides an overview of a rapidly burgeoning field for electronic device engineers, field-based applied physicists, material scientists and nanotechnologists. Furthermore, its clear and concise form equips readers with the basic understanding required to comprehend the present stage of development and to be able to contribute to future development. Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing is also an indispensable resource for students and researchers interested in computer hardware, device physics and circuits design.

Download or read book Near Threshold Computing written by Michael Hübner and published by Springer. This book was released on 2015-11-14 with total page 105 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores near-threshold computing (NTC), a design-space using techniques to run digital chips (processors) near the lowest possible voltage. Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors. Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold manycore chips. · Provides an introduction to near-threshold computing, enabling reader with a variety of tools to face the challenges of the power/utilization wall; · Demonstrates how to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point; · Investigates how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes.

Download or read book Compilers and Operating Systems for Low Power written by Luca Benini and published by Springer Science & Business Media. This book was released on 2011-06-28 with total page 234 pages. Available in PDF, EPUB and Kindle. Book excerpt: Compilers and Operating Systems for Low Power focuses on both application-level compiler directed energy optimization and low-power operating systems. Chapters have been written exclusively for this volume by several of the leading researchers and application developers active in the field. The first six chapters focus on low energy operating systems, or more in general, energy-aware middleware services. The next five chapters are centered on compilation and code optimization. Finally, the last chapter takes a more general viewpoint on mobile computing. The material demonstrates the state-of-the-art work and proves that to obtain the best energy/performance characteristics, compilers, system software, and architecture must work together. The relationship between energy-aware middleware and wireless microsensors, mobile computing and other wireless applications are covered. This work will be of interest to researchers in the areas of low-power computing, embedded systems, compiler optimizations, and operating systems.

Download or read book Computer Architecture Techniques for Power efficiency written by Stefanos Kaxiras and published by Morgan & Claypool Publishers. This book was released on 2008 with total page 220 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics.

Download or read book Reconfigurable Networks on Chip written by Sao-Jie Chen and published by Springer Science & Business Media. This book was released on 2011-12-16 with total page 206 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword: Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers. --Giovanni De Micheli

Download or read book High Performance Energy Efficient Microprocessor Design written by Vojin G. Oklobdzija and published by Springer Science & Business Media. This book was released on 2007-04-27 with total page 342 pages. Available in PDF, EPUB and Kindle. Book excerpt: Written by the world’s most prominent microprocessor design leaders from industry and academia, this book provides complete coverage of all aspects of complex microprocessor design: technology, power management, clocking, high-performance architecture, design methodologies, memory and I/O design, computer aided design, testing and design for testability. The chapters provide state-of-the-art knowledge while including sufficient tutorial material to bring non-experts up to speed. A useful companion to design engineers working in related areas.

Download or read book Energy Efficient High Performance Processors written by Jawad Haj-Yahya and published by Springer. This book was released on 2018-04-04 with total page 165 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

Download or read book Network on Chip Security and Privacy written by Prabhat Mishra and published by Springer Nature. This book was released on 2021-06-04 with total page 496 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides comprehensive coverage of Network-on-Chip (NoC) security vulnerabilities and state-of-the-art countermeasures, with contributions from System-on-Chip (SoC) designers, academic researchers and hardware security experts. Readers will gain a clear understanding of the existing security solutions for on-chip communication architectures and how they can be utilized effectively to design secure and trustworthy systems.

Download or read book ISLPED 04 written by and published by Institute of Electrical & Electronics Engineers(IEEE). This book was released on 2004 with total page 420 pages. Available in PDF, EPUB and Kindle. Book excerpt: "IEEE Catalog Number: 04TH8758"--T.p. verso.

Download or read book Proceedings written by and published by . This book was released on 2004 with total page 424 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book ICT Energy Concepts for Energy Efficiency and Sustainability written by Giorgos Fagas and published by BoD – Books on Demand. This book was released on 2017-03-22 with total page 252 pages. Available in PDF, EPUB and Kindle. Book excerpt: In a previous volume (ICT-Energy-Concepts Towards Zero-Power ICT; referenced below as Vol. 1), we addressed some of the fundamentals related to bridging the gap between the amount of energy required to operate portable/mobile ICT systems and the amount of energy available from ambient sources. The only viable solution appears to be to attack the gap from both sides, i.e. to reduce the amount of energy dissipated during computation and to improve the efficiency in energy-harvesting technologies. In this book, we build on those concepts and continue the discussion on energy efficiency and sustainability by addressing the minimisation of energy consumption at different levels across the ICT system stack, from hardware to software, as well as discussing energy consumption issues in high-performance computing (HPC), data centres and communication in sensor networks. This book was realised thanks to the contribution of the project ‘Coordinating Research Efforts of the ICT-Energy Community’ funded from the European Union under the Future and Emerging Technologies (FET) area of the Seventh Framework Programme for Research and Technological Development (grant agreement n. 611004).