Download or read book Energy Efficient Computing Through Compiler Assisted Dynamic Specialization written by and published by . This book was released on 2014 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Due to the failure of threshold voltage scaling, per-transistor switching power is not scaling down at the pace of Moore's Law, causing the power density to rise for each successive generation. Consequently, computer architects need to improve the energy efficiency of microarchitecture designs to sustain the traditional performance growth. Hardware specialization or using accelerators is a promising direction to improve the energy efficiency without sacrificing performance. However, it requires disruptive changes in hardware and software including the programming model, applications, and operating systems. Moreover, specialized accelerators cannot help with the general purpose computing. Going forward, we need a solution that avoids such disruptive changes and can accelerate or specialize even general purpose workloads. This thesis develops a hardware/software co-designed solution called Dynamically Specialized Execution, which uses compiler assisted dynamic specialization to improve the energy efficiency without radical changes to microarchitecture, the ISA or the programming model. This dissertation first develops a decoupled access/execute coarse-grain reconfigurable architecture called DySER: Dynamically Specialized Execution Resources, which achieves energy efficiency by creating specialized hardware at runtime for hot code regions. DySER exposes a well defined interface and execution model, which makes it easier to integrate DySER with an existing core microarchitecture. To address the challenges of compiling for a specialized accelerator, this thesis develops a novel compiler intermediate representation called the Access/Execute Program Dependence Graph (AEPDG), which accurately models DySER and captures the spatio-temporal aspects of its execution. This thesis shows that using this representation, we can implement a compiler that generates highly optimized code for a coarse-grain reconfigurable architecture without manual intervention for programs written in the traditional programming model. Detailed evaluation shows that automatic specialization of data parallel workloads with DySER provides a mean speedup of 3.8x with 60% energy reduction when compared to a 4-wide out-of-order processor. On irregular workloads, exemplified by SPECCPU, DySER provides on average speedup of 11% with 10% reduction in energy consumption. On a highly relevant application, database query processing, which has a mix of data parallel kernels and irregular kernels, DySER provides an 2.7x speedup over the 4-wide out-of-order processor.

Download or read book Energy Efficient High Performance Processors written by Jawad Haj-Yahya and published by Springer. This book was released on 2018-03-22 with total page 176 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

Download or read book Energy Efficient Computing Using Static dynamic Co optimizations written by Karthik Gururaj and published by . This book was released on 2013 with total page 150 pages. Available in PDF, EPUB and Kindle. Book excerpt: Energy consumption is a primary concern of current day computing systems -- from handheld battery operated systems to servers in data centers connected to wall power. Research in academia as well as industry has focused on a variety of techniques for minimizing energy consumption while maintaining a good level of performance. The most effective techniques combine the best of static (or offline) and dynamic (or online/runtime) optimizations to obtain the best solution. Static optimizations can be more complex and can afford to take a global view of the application/computation being executed on the system -- however, such optimizations have to be conservative in nature because they cannot anticipate all the different scenarios that can appear at runtime. Dynamic optimizations have more information about the application/computation for the given input -- however, since such optimizations have to have low overhead, they can afford to have only a local view of the computation/ application and the complexity of the optimization has to be relatively low. An additional direction that needs to be considered is to determine whether dynamic optimizations should be implemented in software or hardware. In this thesis, I present a study of three aspects of energy efficient computing that use a combination of static and dynamic optimizations to minimize energy consumption. The first aspect is to consider variability in the execution time of applications during scheduling for dynamic voltage frequency scaling (DVFS) capable systems to minimize energy consumption and yet maintain a desired level of performance. The main idea is to construct a schedule table offline and perform a simple table look-up at runtime. The second aspect is to consider application-level reliability for applications that can tolerate certain error in the outputs. I present the study of a profile-guided offline compilation strategy to identify critical instructions and a monitoring technique in software to handle corner cases at runtime. Finally, the third aspect of energy efficient computing I investigate is flexibility customizing the instruction sets of processors to improve energy efficiency. I study the benefits of compiler directed optimizations for generating custom instructions which are executed within a modified processor pipeline and an architecture mechanism for detecting corner cases and to roll-back to a safe state. Additionally, I investigate the benefits of customizing the instruction set dynamically in hardware.

Download or read book Mechanisms Towards Energy efficient Dynamic Hardware Specialization written by and published by . This book was released on 2014 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the past few decades, Von Neumann superscalar processors have been the prevalent approach for general purpose processing. Hardware specialization, as a complementary technique, offers superior performance, power or energy efficiency on specific tasks. Today, with an increased focus on energy critical platforms such as datacenters and mobile devices, hardware specialization are becoming an important and widely used approach to improving the overall efficiency. Our work is motivated by observing that in frequent program phases, using specialized hardware could eliminate the conventional "instruction processing" in a superscalar pipeline. To this end, we propose two supporting architectures, for both computation and data acquisition, under a hardware-software co-designed execution model- Dynamically Specialized Execution (DySE). This model leverages re-configurable hardware and decoupled access/execute for energy efficiency, generality and flexibility. The two architectures discussed in this dissertation are: Dynamically Specialized Execution Resources (DySER) and Memory Access Dataflow (MAD). Decoupling access and execute components in a program phase enables different optimization opportunities in hardware. DySER, the supporting architecture for the execute component, is a circuit-switched functional unit fabric that can be viewed as a long-latency, multi-input and asynchronous unit. MAD, on the other hand, is an event-driven dataflow memory access engine. It efficiently performs two primitive tasks found in a superscalar processor: (1) computations that generate recurring address patterns/branches; (2) event-condition evaluations that trigger resulting data movements. By turning off the host, using MAD to drive the accelerators delivers energy improvement compared to an out-of-order host processor. This dissertation has the following findings: First, we prove that DySER is a viable approach by building a SPARC-DySER prototype, which integrates DySER into OpenSPARC. In the eval- uation of DySER, we observe 80% saving in dynamic instruction count, 3.47x speedup and 3.55x energy reduction over a power-efficient 2-issue out-of-order processor; DySER increases the parallelism for such speedup through its hardware, vector interface, and decoupled ac- cess/execute. Second, we support DySER with MAD and increase the overall speedup and energy reduction over the same base to 5.3x and 5.6x respectively. MAD can also drive other execute accelerators or perform access-only codes for energy-efficiency. Compared to a 2-issue superscalar host, MAD increases the parallelism and lowers the power consumption through its microarchitecture, which benefits from the exposure of computation, dataflow events and actions in the MAD ISA.

Download or read book Energy efficient Computing with Fine grained Many core Systems written by Bin Liu and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: For the past half century, Moore's Law has been the fundamental driver of high-performance computing. The continued CMOS technology scaling doubles the transistor density of VLSI systems and had provided a predictable 40% performance improvement of single-core processors for every 18 to 24 months. However, as Dennard Scaling ends, the era of scaling frequency and performance without increasing power density is over. Since 2005, the semiconductor industry shifted to multi-core and many-core processors in order to sustain the proportional scaling of performance along with transistor count increases. One of the critical challenges for many-core system design is to reduce the power dissipation and improve the energy efficiency of the chip. Researchers are eager to seek innovative low power architectures and techniques to relieve the ``dark silicon" problem and effectively convert transistors to performance. To demonstrate that many-core processors with network-on-chip interconnects is a promising architecture for high-performance energy-efficient computing, 16 Advanced Encryption Standard (AES) engines are proposed on a fine-grained many-core system by exploring different granularities of data-level and task-level parallelism. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 cores and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, the designs have has 3.5--15.6 times higher throughput per unit of chip area and 8.2--18.1 times higher energy efficiency. Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per unit of chip area and 2.9 times higher energy efficiency than the GeForce 8800 GTX. Next, a scalable joint local and global dynamic voltage and frequency scaling (DVFS) scheme is proposed to further improve the energy efficiency for many-core systems by monitoring on-line workload variations. The local algorithms selects the voltage and frequency pair for each individual core based on its FIFO occupancy and stall information, while the global algorithm tunes the global voltage supplies based on the workload of all active processors. To demonstrate the effectiveness of the proposed solution, a suite of benchmarks are tested on a many-core globally asynchronous locally synchronous (GALS) platform. The experiment results show that the proposed approach can achieve near-optimal power saving under performance constraints. Different local algorithms are compared in terms of power saving, voltage switching frequency and response delay to workload variation. The impact of the number of voltage supplies and global voltage tuning resolution on the global algorithm is also investigated. To further improve the energy efficiency beyond traditional DVFS, core scaling is proposed by introducing an extra dimension beyond supply voltage and clock frequency scaling. This dissertation addresses the problem of minimizing the power dissipation of many-core systems under performance constraints by choosing an appropriate number of active cores and per-core voltage/frequency levels. A genetic algorithm based solution is proposed to solve the problem. Experiments with real applications show that (1) dynamically scaling the number of active cores can improve the energy efficiency by 5% to 42% compared with per-core DVFS for different performance requirements; (2) core scaling favors systems with more global voltage supplies and high-performance leaky process when the performance requirement is loose, while it favors systems with fewer global voltage supplies and low-power less-leaky process when the performance requirement is tight; (3) increasing the number of global voltage supplies or leakage ratio can reduce the optimal core count by 22% and 50%, respectively.

Download or read book Hardware assisted Fast Routing for Runtime Reconfigurable Computing written by Randy Ren-Fu Huang and published by . This book was released on 2004 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Masters Theses in the Pure and Applied Sciences written by Wade H. Shafer and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 421 pages. Available in PDF, EPUB and Kindle. Book excerpt: Masters Theses in the Pure and Applied Sciences was first conceived, published, and disseminated by the Center for Information and Numerical Data Analysis and Synthesis (CINDAS) * at Purdue University in 1957, starting its coverage of theses with the academic year 1955. Beginning with Volume 13, the printing and dissemination phases of the activity were transferred to University Microfilms/Xerox of Ann Arbor, Michigan, with the thought that such an arrangement would be more beneficial to the academic and general scientific and technical community. After five years of this joint undertaking we had concluded that it was in the interest of all con cerned if the printing and distribution of the volumes were handled by an interna tional publishing house to assure improved service and broader dissemination. Hence, starting with Volume 18, Masters Theses in the Pure and Applied Sciences has been disseminated on a worldwide basis by Plenum Publishing Cor poration of New York, and in the same year the coverage was broadened to include Canadian universities. All back issues can also be ordered from Plenum. We have reported in Volume 34 (thesis year 1989) a total of 13,377 theses titles from 26 Canadian and 184 United States universities. We are sure that this broader base for these titles reported will greatly enhance the value of this important annual reference work. While Volume 34 reports theses submitted in 1989, on occasion, certain univer sities do report theses submitted in previous years but not reported at the time.

Download or read book High Performance Embedded Architectures and Compilers written by Per Stenström and published by Springer. This book was released on 2008-01-18 with total page 399 pages. Available in PDF, EPUB and Kindle. Book excerpt: This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field.

Download or read book 31st Annual International Symposium on Computer Architecture written by and published by Institute of Electrical & Electronics Engineers(IEEE). This book was released on 2004 with total page 412 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Handbook of Research on Developments and Trends in Industrial and Materials Engineering written by Sahoo, Prasanta and published by IGI Global. This book was released on 2019-11-01 with total page 524 pages. Available in PDF, EPUB and Kindle. Book excerpt: In today’s modernized world, new research and empirical findings are being conducted and found within various professional industries. The field of engineering is no different. Industrial and material engineering is continually advancing, making it challenging for practitioners to keep pace with the most recent trends and methods. Engineering professionals need a handbook that provides up-to-date research on the newest methodologies in this imperative industry. The Handbook of Research on Developments and Trends in Industrial and Materials Engineering is a collection of innovative research on the theoretical and practical aspects of integrated systems within engineering. This book provides a forum for professionals to understand the advancing methods of engineering. While highlighting topics including operations management, decision analysis, and communication technology, this book is ideally designed for researchers, managers, engineers, industrialists, manufacturers, academicians, policymakers, scientists, and students seeking current research on recent findings and modern approaches within industrial and materials engineering.

Download or read book Energy Abstracts for Policy Analysis written by and published by . This book was released on 1979 with total page 1106 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Innovations and Approaches for Resilient and Adaptive Systems written by De Florio, Vincenzo and published by IGI Global. This book was released on 2012-09-30 with total page 398 pages. Available in PDF, EPUB and Kindle. Book excerpt: Our society continues to depend upon systems that are built in a way that they end up being inflexible and intolerant to change. Therefore there is an urgent need to investigate innovations and approaches to the management of adaptive and dependable systems. These studies are usually implemented through design, development, and the evaluation of techniques and models to structure computer systems as adaptive systems. Innovations and Approaches for Resilient and Adaptive Systems is a comprehensive collection of knowledge on increasing the notions and models in adaptive and dependable systems. This book aims to enhance the awareness of the role of adaptability and resilience in system environments for researchers, practitioners, educators, and professionals alike.

Download or read book Reconfigurable Computing Systems Engineering written by Lev Kirischian and published by CRC Press. This book was released on 2017-12-19 with total page 241 pages. Available in PDF, EPUB and Kindle. Book excerpt: Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture describes the organization of reconfigurable computing system (RCS) architecture and discusses the pros and cons of different RCS architecture implementations. Providing a solid understanding of RCS technology and where it’s most effective, this book: Details the architecture organization of RCS platforms for application-specific workloads Covers the process of the architectural synthesis of hardware components for system-on-chip (SoC) for the RCS Explores the virtualization of RCS architecture from the system and on-chip levels Presents methodologies for RCS architecture run-time integration according to mode of operation and rapid adaptation to changes of multi-parametric constraints Includes illustrative examples, case studies, homework problems, and references to important literature A solutions manual is available with qualifying course adoption. Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture offers a complete road map to the synthesis of RCS architecture, exposing hardware design engineers, system architects, and students specializing in designing FPGA-based embedded systems to novel concepts in RCS architecture organization and virtualization.

Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1995 with total page 702 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Embedded System Design written by Peter Marwedel and published by Springer. This book was released on 2017-07-26 with total page 442 pages. Available in PDF, EPUB and Kindle. Book excerpt: A unique feature of this textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This third edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems and the Internet of things, the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues.

Download or read book Government Reports Announcements Index written by and published by . This book was released on 1993 with total page 1528 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Generative Programming and Component Engineering written by Don Batory and published by Springer Science & Business Media. This book was released on 2002-09-23 with total page 344 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the ACM SIGPLAN/SIGSOFT Conference on Generative Programming and Component Engineering, GPCE 2002, held in Pittsburgh, PA, USA in October 2002. The 18 revised full papers presented were carefully reviewed and selected from 39 submissions. Among the topics covered are generative programming, meta-programming, program specialization, program analysis, program transformation, domain-specific languages, software architectures, aspect-oriented programming, and component-based systems.