Download or read book Efficient VLSI Very Large Scale Integration Fault Simulation written by J. H. Reif and published by . This book was released on 1985 with total page 47 pages. Available in PDF, EPUB and Kindle. Book excerpt: Let C be an acyclic boolean circuit with n gates and equal to or less than n inputs. A circuit manufacture error may result in a Stuck-at (S-A) fault is a circuit identical to C except a gate v only outputs a fixed boolean value. The (S-A) fault simulation problem for C is to determine all possible S-A faults which can be detected (i.e., faults for which a faulty circuit and C would give distinct outputs) by a given test pattern input. We consider the case where C is a tree (i.e., has fan-out 1). We give practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C. Our algorithm requires only the evaluation of a circuit FS(C) which has equal to or less than 3(d+1), when d is the depth of C. Thus the sequential time of our algorithm is equal to or less than 7n, and the parallel time is equal to or less than 3(d+1). Furthermore FS(C) requires only a small constant factor more VLSI area than does the original circuit C. We also extend our results to get efficient methods for fault simulation of oblivious VLSI circuits with feedback lines. Originator supplied keywords include: VLSI; fault simulation; stuck-at faults; reliable computation; boolean functions; partial derivations; and boolean circuits.

Download or read book Testing and Diagnosis of VLSI and ULSI written by F. Lombardi and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 531 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume contains a collection of papers presented at the NATO Advanced Study Institute on ·Testing and Diagnosis of VLSI and ULSI" held at Villa Olmo, Como (Italy) June 22 -July 3,1987. High Density technologies such as Very-Large Scale Integration (VLSI), Wafer Scale Integration (WSI) and the not-so-far promises of Ultra-Large Scale Integration (ULSI), have exasperated the problema associated with the testing and diagnosis of these devices and systema. Traditional techniques are fast becoming obsolete due to unique requirements such as limited controllability and observability, increasing execution complexity for test vector generation and high cost of fault simulation, to mention just a few. New approaches are imperative to achieve the highly sought goal of the • three months· turn around cycle time for a state-of-the-art computer chip. The importance of testing and diagnostic processes is of primary importance if costs must be kept at acceptable levels. The objective of this NATO-ASI was to present, analyze and discuss the various facets of testing and diagnosis with respect to both theory and practice. The contents of this volume reflect the diversity of approaches currently available to reduce test and diagnosis time. These approaches are described in a concise, yet clear way by renowned experts of the field. Their contributions are aimed at a wide readership: the uninitiated researcher will find the tutorial chapters very rewarding. The expert wiII be introduced to advanced techniques in a very comprehensive manner.

Download or read book VLSI Systems on a Chip written by Luis Miguel Silveira and published by Springer. This book was released on 2013-11-11 with total page 692 pages. Available in PDF, EPUB and Kindle. Book excerpt: For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.

Download or read book Advanced Simulation and Test Methodologies for VLSI Design written by G. Russell and published by Springer Science & Business Media. This book was released on 1989-02-28 with total page 406 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1995 with total page 704 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Hierarchical Modeling for VLSI Circuit Testing written by Debashis Bhattacharya and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

Download or read book Efficient VLSI Fault Simulation written by John H. Reif and published by . This book was released on 1985 with total page 29 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Unified Methods for VLSI Simulation and Test Generation written by Kwang-Ting (Tim) Cheng and published by Springer. This book was released on 1989-06-30 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book VLSI Fault Modeling and Testing Techniques written by George W. Zobrist and published by Praeger. This book was released on 1993 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.

Download or read book Electrothermal Analysis of VLSI Systems written by Yi-Kan Cheng and published by Springer Science & Business Media. This book was released on 2005-12-01 with total page 220 pages. Available in PDF, EPUB and Kindle. Book excerpt: This useful book addresses electrothermal problems in modern VLSI systems. It discusses electrothermal phenomena and the fundamental building blocks that electrothermal simulation requires. The authors present three important applications of VLSI electrothermal analysis: temperature-dependent electromigration diagnosis, cell-level thermal placement, and temperature-driven power and timing analysis.

Download or read book Computer Aided Tools for VLSI System Design written by Gordon Russell and published by P. Peregrinus. This book was released on 1987 with total page 220 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Computer Design Aids for VLSI Circuits written by P. Antognetti and published by Springer Science & Business Media. This book was released on 2013-11-11 with total page 543 pages. Available in PDF, EPUB and Kindle. Book excerpt: The Nato Advanced Study Institute on "Computer Design Aids for VLSI Circuits" was held from July 21 to August 1, 1980 at Sogesta, Urbino, Italy. Sixty-three carefully chosen profes sionals were invited to participate in this institute together with 12 lecturers and 7 assistants. The 63 participants were selected from a group of almost 140 applicants. Each had the background to learn effectively the set of computer IC design aids which were presented. Each also had individual expertise in at least one of the topics of the Institute. The Institute was designed to provide hands-on type of experience rather than consisting of solely lecture and discussion. Each morning, detailed presentations were made concerning the critical algorithms that are used in the various types of computer IC design aids. Each afternoon a lengthy period was used to provide the participants with direct access to the computer programs. In addition to using the programs, the individual could, if his expertise was sufficient, make modifications of and extensions to the programs, or establish limitations of these present aids. The interest in this hands-on activity was very high and many participants worked with the programs every free hour. The editors would like to thank the Direction of SOGESTA for the excellent facilities, ~1r. R. Riccioni of the SOGESTA Computer Center and Mr. 11. Vanzi of the University of Genova for enabling all the programs to run smoothly on the set date. P.Antognetti D.O.Pederson Urbino, Summer 1980.

Download or read book Defect and Fault Tolerance in VLSI Systems written by C.H. Stapper and published by Springer Science & Business Media. This book was released on 2013-06-29 with total page 313 pages. Available in PDF, EPUB and Kindle. Book excerpt: Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.

Download or read book Relaxation Techniques for the Simulation of VLSI Circuits written by Jacob K. White and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 202 pages. Available in PDF, EPUB and Kindle. Book excerpt: Circuit simulation has been a topic of great interest to the integrated circuit design community for many years. It is a difficult, and interesting, problem be cause circuit simulators are very heavily used, consuming thousands of computer hours every year, and therefore the algorithms must be very efficient. In addi tion, circuit simulators are heavily relied upon, with millions of dollars being gambled on their accuracy, and therefore the algorithms must be very robust. At the University of California, Berkeley, a great deal of research has been devoted to the study of both the numerical properties and the efficient imple mentation of circuit simulation algorithms. Research efforts have led to several programs, starting with CANCER in the 1960's and the enormously successful SPICE program in the early 1970's, to MOTIS-C, SPLICE, and RELAX in the late 1970's, and finally to SPLICE2 and RELAX2 in the 1980's. Our primary goal in writing this book was to present some of the results of our current research on the application of relaxation algorithms to circuit simu lation. As we began, we realized that a large body of mathematical and exper imental results had been amassed over the past twenty years by graduate students, professors, and industry researchers working on circuit simulation. It became a secondary goal to try to find an organization of this mass of material that was mathematically rigorous, had practical relevance, and still retained the natural intuitive simplicity of the circuit simulation subject.

Download or read book Very Large Scale Integration VLSI written by D.F. Barbe and published by Springer. This book was released on 1982 with total page 330 pages. Available in PDF, EPUB and Kindle. Book excerpt: With contributions by numerous experts

Download or read book VLSI Chip Design with the Hardware Description Language VERILOG written by Ulrich Golze and published by Springer Science & Business Media. This book was released on 2013-11-11 with total page 363 pages. Available in PDF, EPUB and Kindle. Book excerpt: The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book. After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.