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Book Efficient VLSI Fault Simulation

Download or read book Efficient VLSI Fault Simulation written by John H. Reif and published by . This book was released on 1985 with total page 29 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Efficient VLSI Very Large Scale Integration Fault Simulation

Download or read book Efficient VLSI Very Large Scale Integration Fault Simulation written by J. H. Reif and published by . This book was released on 1985 with total page 47 pages. Available in PDF, EPUB and Kindle. Book excerpt: Let C be an acyclic boolean circuit with n gates and equal to or less than n inputs. A circuit manufacture error may result in a Stuck-at (S-A) fault is a circuit identical to C except a gate v only outputs a fixed boolean value. The (S-A) fault simulation problem for C is to determine all possible S-A faults which can be detected (i.e., faults for which a faulty circuit and C would give distinct outputs) by a given test pattern input. We consider the case where C is a tree (i.e., has fan-out 1). We give practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C. Our algorithm requires only the evaluation of a circuit FS(C) which has equal to or less than 3(d+1), when d is the depth of C. Thus the sequential time of our algorithm is equal to or less than 7n, and the parallel time is equal to or less than 3(d+1). Furthermore FS(C) requires only a small constant factor more VLSI area than does the original circuit C. We also extend our results to get efficient methods for fault simulation of oblivious VLSI circuits with feedback lines. Originator supplied keywords include: VLSI; fault simulation; stuck-at faults; reliable computation; boolean functions; partial derivations; and boolean circuits.

Book Efficient Modeling Techniques for Fault Simulation of Large Circuits

Download or read book Efficient Modeling Techniques for Fault Simulation of Large Circuits written by Lavanya Rachel Cherian and published by . This book was released on 1989 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Advanced Simulation and Test Methodologies for VLSI Design

Download or read book Advanced Simulation and Test Methodologies for VLSI Design written by G. Russell and published by Springer Science & Business Media. This book was released on 1989-02-28 with total page 406 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Delay Fault Testing for VLSI Circuits

Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Book VLSI Systems on a Chip

Download or read book VLSI Systems on a Chip written by Luis Miguel Silveira and published by Springer. This book was released on 2013-11-11 with total page 692 pages. Available in PDF, EPUB and Kindle. Book excerpt: For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.

Book Speeding Up Logic Level Fault Simulation Using Efficient Module Representations

Download or read book Speeding Up Logic Level Fault Simulation Using Efficient Module Representations written by Ruth Iris Bahar and published by . This book was released on 1987 with total page 106 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book An Efficient Logic Fault Diagnosis Framework Based on Effect cause Approach

Download or read book An Efficient Logic Fault Diagnosis Framework Based on Effect cause Approach written by Lei Wu and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise.

Book Testing and Diagnosis of VLSI and ULSI

Download or read book Testing and Diagnosis of VLSI and ULSI written by F. Lombardi and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 531 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume contains a collection of papers presented at the NATO Advanced Study Institute on ·Testing and Diagnosis of VLSI and ULSI" held at Villa Olmo, Como (Italy) June 22 -July 3,1987. High Density technologies such as Very-Large Scale Integration (VLSI), Wafer Scale Integration (WSI) and the not-so-far promises of Ultra-Large Scale Integration (ULSI), have exasperated the problema associated with the testing and diagnosis of these devices and systema. Traditional techniques are fast becoming obsolete due to unique requirements such as limited controllability and observability, increasing execution complexity for test vector generation and high cost of fault simulation, to mention just a few. New approaches are imperative to achieve the highly sought goal of the • three months· turn around cycle time for a state-of-the-art computer chip. The importance of testing and diagnostic processes is of primary importance if costs must be kept at acceptable levels. The objective of this NATO-ASI was to present, analyze and discuss the various facets of testing and diagnosis with respect to both theory and practice. The contents of this volume reflect the diversity of approaches currently available to reduce test and diagnosis time. These approaches are described in a concise, yet clear way by renowned experts of the field. Their contributions are aimed at a wide readership: the uninitiated researcher will find the tutorial chapters very rewarding. The expert wiII be introduced to advanced techniques in a very comprehensive manner.

Book Hierarchical Modeling for VLSI Circuit Testing

Download or read book Hierarchical Modeling for VLSI Circuit Testing written by Debashis Bhattacharya and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

Book VLSI Test Principles and Architectures

Download or read book VLSI Test Principles and Architectures written by Laung-Terng Wang and published by Elsevier. This book was released on 2006-08-14 with total page 809 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Book Scientific and Technical Aerospace Reports

Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1994 with total page 652 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Book Test Generation of Crosstalk Delay Faults in VLSI Circuits

Download or read book Test Generation of Crosstalk Delay Faults in VLSI Circuits written by S. Jayanthy and published by Springer. This book was released on 2018-09-20 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

Book VLSI Circuit Simulation and Optimization

Download or read book VLSI Circuit Simulation and Optimization written by V. Litovski and published by Springer Science & Business Media. This book was released on 1996-12-31 with total page 370 pages. Available in PDF, EPUB and Kindle. Book excerpt: Circuit simulation has become an essential tool in circuit design and without it's aid, analogue and mixed-signal IC design would be impossible. However the applicability and limitations of circuit simulators have not been generally well understood and this book now provides a clear and easy to follow explanation of their function. The material covered includes the algorithms used in circuit simulation and the numerical techniques needed for linear and non-linear DC analysis, transient analysis and AC analysis. The book goes on to explain the numeric methods to include sensitivity and tolerance analysis and optimisation of component values for circuit design. The final part deals with logic simulation and mixed-signal simulation algorithms. There are comprehensive and detailed descriptions of the numerical methods and the material is presented in a way that provides for the needs of both experienced engineers who wish to extend their knowledge of current tools and techniques, and of advanced students and researchers who wish to develop new simulators.