Download or read book Efficient Techniques for Modeling and Mitigation of Soft Errors in Nanometer scale Static CMOS Logic Circuits written by Srivathsan Krishnamohan and published by . This book was released on 2005 with total page 282 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Soft Error Reliability of VLSI Circuits written by Behnam Ghavami and published by Springer Nature. This book was released on 2020-10-13 with total page 114 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is intended for readers who are interested in the design of robust and reliable electronic digital systems. The authors cover emerging trends in design of today’s reliable electronic systems which are applicable to safety-critical applications, such as automotive or healthcare electronic systems. The emphasis is on modeling approaches and algorithms for analysis and mitigation of soft errors in nano-scale CMOS digital circuits, using techniques that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. The authors introduce software tools for analysis and mitigation of soft errors in electronic systems, which can be integrated easily with design flows. In addition to discussing soft error aware analysis techniques for combinational logic, the authors also describe new soft error mitigation strategies targeting commercial digital circuits. Coverage includes novel Soft Error Rate (SER) analysis techniques such as process variation aware SER estimation and GPU accelerated SER analysis techniques, in addition to SER reduction methods such as gate sizing and logic restructuring based SER techniques.
Download or read book Advances in Wireless Mobile Networks and Applications written by Salah S. Al-Majeed and published by Springer Science & Business Media. This book was released on 2011-05-10 with total page 329 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Third International Conference on Wireless, Mobile Networks and Applications, WiMoA 2011, and the First International Conference on Computer Science, Engineering and Applications, ICCSEA 2011, held in Dubai, United Arab Emirates, in May 2011. The book is organized as a collection of papers from WiMoA 2011 and ICCSEA 2011. The 8 revised full papers presented in the WiMoA 2011 part were carefully reviewed and selected from 63 submissions. The 20 revised full papers presented in the ICCSEA 2011 part were carefully reviewed and selected from 110 submissions.
Download or read book Architectures and Algorithms for Mitigation of Soft Errors in Nanoscale VLSI Circuits written by Koustav Bhattacharya and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: ABSTRACT: The occurrence of transient faults like soft errors in computer circuits poses a significant challenge to the reliability of computer systems. Soft error, which occurs when the energetic neutrons coming from space or the alpha particles arising out of packaging materials hit the transistors, may manifest themselves as a bit flip in the memory element or as a transient glitch generated at any internal node of combinational logic, which may subsequently propagate to and be captured in a latch. Although the problem of soft errors was earlier only a concern for space applications, aggressive technology scaling trends have exacerbated the problem to modern VLSI systems even for terrestrial applications. In this dissertation, we explore techniques at all levels of the design flow to reduce the vulnerability of VLSI systems against soft errors without compromising on other design metrics like delay, area and power. We propose new models for estimating soft errors for storage structures and combinational logic. While soft errors in caches are estimated using the vulnerability metric, soft errors in logic circuits are estimated using two new metrics called the glitch enabling probability (GEP) and the cumulative probability of observability (CPO). These metrics, based on signal probabilities of nets, accurately model soft errors in radiation-aware synthesis algorithms and helps in efficient exploration of the design solution space during optimization. At the physical design level, we leverage the use of larger netlengths to provide larger RC ladders for effectively filtering out the transient glitches. Towards this, a new heuristic has been developed to selectively assign larger wirelengths to certain critical nets. This reduces the delay and area overhead while improving the immunity to soft errors. Based on this, we propose two placement algorithms based on simulated annealing and quadratic programming which significantly reduce the soft error rates of circuits. At the circuit level, we develop techniques for hardening circuit nodes using a novel radiation jammer technique. The proposed technique is based on the principles of a RC differentiator and is used to isolate the driven cell from the driving cell which is being hit by a radiation strike. Since the blind insertion of radiation blocker cells on all circuit nodes is expensive, candidate nodes are selected for insertion of these cells using a new metric called the probability of radiation blocker circuit insertion (PRI). We investigate a gate sizing algorithm, at the logic level, in which we simultaneously optimize both the soft error rate (SER) and the crosstalk noise besides the power and performance of circuits while considering the effect of process variations. The reliability centric gate sizing technique has been formulated as a mathematical program and is efficiently solved. At the architectural level, we develop solutions for the correction of multi-bit errors in large L2 caches by controlling or mining the redundancy in the memory hierarchy and methods to increase the amount of redundancy in the memory hierarchy by employing a redundancy-based replacement policy, in which the amount of redundancy is controlled using a user defined redundancy threshold. The novel architectures and the new reliability-centric synthesis algorithms proposed for the various design abstraction levels have been shown to achieve significant reduction of soft error rates in current nanometer circuits. The design techniques, algorithms and architectures can be integrated into existing design flows. A VLSI system implementation can leverage on the architectural solutions for the reliability of the caches while the custom hardware synthesized for the VLSI system can be protected against radiation strikes by utilizing the circuit level, logic level and layout level optimization algorithms that have been developed.
Download or read book Soft Errors in Modern Electronic Systems written by Michael Nicolaidis and published by Springer Science & Business Media. This book was released on 2010-09-24 with total page 331 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a comprehensive presentation of the most advanced research results and technological developments enabling understanding, qualifying and mitigating the soft errors effect in advanced electronics, including the fundamental physical mechanisms of radiation induced soft errors, the various steps that lead to a system failure, the modelling and simulation of soft error at various levels (including physical, electrical, netlist, event driven, RTL, and system level modelling and simulation), hardware fault injection, accelerated radiation testing and natural environment testing, soft error oriented test structures, process-level, device-level, cell-level, circuit-level, architectural-level, software level and system level soft error mitigation techniques. The book contains a comprehensive presentation of most recent advances on understanding, qualifying and mitigating the soft error effect in advanced electronic systems, presented by academia and industry experts in reliability, fault tolerance, EDA, processor, SoC and system design, and in particular, experts from industries that have faced the soft error impact in terms of product reliability and related business issues and were in the forefront of the countermeasures taken by these companies at multiple levels in order to mitigate the soft error effects at a cost acceptable for commercial products. In a fast moving field, where the impact on ground level electronics is very recent and its severity is steadily increasing at each new process node, impacting one after another various industry sectors (as an example, the Automotive Electronics Council comes to publish qualification requirements on soft errors), research and technology developments and industrial practices have evolve very fast, outdating the most recent books edited at 2004.
Download or read book Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits written by Hsiao-Heng Kelin Lee and published by Stanford University. This book was released on 2011 with total page 156 pages. Available in PDF, EPUB and Kindle. Book excerpt: Radiation-induced soft errors are a major concern for modern digital circuits, especially memory elements. Unlike large Random Access Memories that can be protected using error-correcting codes and bit interleaving, soft error protection of sequential elements, i.e. latches and flip-flops, is challenging. Traditional techniques for designing soft-error-resilient sequential elements generally address single node errors, or Single Event Upsets (SEUs). However, with technology scaling, the charge deposited by a single particle strike can be simultaneously collected and shared by multiple circuit nodes, resulting in Single Event Multiple Upsets (SEMUs). In this work, we target SEMUs by presenting a design framework for soft-error-resilient sequential cell design with an overview of existing circuit and layout techniques for soft error mitigation, and introducing a new soft error resilience layout design principle called LEAP, or Layout Design through Error-Aware Transistor Positioning. We then discuss our application of LEAP to the SEU-immune Dual Interlocked Storage Cell (DICE) by implementing a new sequential element layout called LEAP-DICE, retaining the original DICE circuit topology. We compare the soft error performance of SEU-immune flip-flops with the LEAP-DICE flip-flop using a test chip in 180nm CMOS under 200-MeV proton radiation and conclude that 1) our LEAP-DICE flip-flop encounters on average 2,000X and 5X fewer errors compared to a conventional D flip-flop and our reference DICE flip-flop, respectively; 2) our LEAP-DICE flip-flop has the best soft error performance among all existing SEU-immune flip-flops; 3) In the evaluation of our design framework, we also discovered new soft error effects related to operating conditions such as voltage scaling, clock frequency setting and radiation dose.
Download or read book A Methodology for Characterization Modeling and Mitigation of Single Event Transient Effects in CMOS Standard Combinational Cells written by Marko Andjelković and published by . This book was released on 2021 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the downscaling of CMOS technologies, the radiation-induced Single Event Transient (SET) effects in combinational logic have become a critical reliability issue for modern integrated circuits (ICs) intended for operation under harsh radiation conditions. The SET pulses generated in combinational logic may propagate through the circuit and eventually result in soft errors. It has thus become an imperative to address the SET effects in the early phases of the radiation-hard IC design. In general, the soft error mitigation solutions should accommodate both static and dynamic measures to ensure the optimal utilization of available resources. An efficient soft-error-aware design should address synergistically three main aspects: (i) characterization and modeling of soft errors, (ii) multi-level soft error mitigation, and (iii) online soft error monitoring. Although significant results have been achieved, the effectiveness of SET characterization methods, accuracy of predictive SET models, and efficiency of SET mitigation measures are ...
Download or read book Reliability Improvement Against Soft Errors in Nanometer Digital Circuits written by and published by . This book was released on 2012 with total page 162 pages. Available in PDF, EPUB and Kindle. Book excerpt: As technology nodes are shrinking to nanometers, handling soft errors due to particle strikes in digital circuits is becoming increasingly challenging. Most of the previously proposed techniques for soft error rate reduction require high cost in terms of circuit performance penalty and area overhead. This study explores the effect of soft errors on nanometer circuits, develops soft error models, and proposes novel mitigation techniques for adaption in combinational and sequential circuits. For combinational logic circuits, we first develop a simulator which takes into consideration gate/circuit input dependence of soft errors. Our methods to reduce soft error rate in combinational circuits include an overhead free technique called gate input reconfiguration, which can assign the best input configuration for soft error hardening, and two sizing based techniques employing optimization formulation and heuristics. Moreover, to improve reliability due to combinative effect of leakage and soft errors in logic circuits, we develop a novel way of combining the two into a single metric, mean time to failure (MTTF) and we introduce an optimal and a heuristic solution that maximize the overall MTTF through body bias. For sequential circuits, we develop a simulator which includes input dependence of soft errors and all masking probabilities, such as electrical masking, logical masking and timing window masking. In this part, we propose an optimal flip-flop selection for soft error detection which is formulated as a binary integer linear programing (BILP) problem. This approach ensures that maximum soft error detection can be achieved for a given number of selected flip-flops. Consequently, we define a new metric called re-execution penalty index which represents the time penalty required to recover from a soft error. We further develop a combined flip-flop selection and gate sizing technique which uses the re-execution penalty index to identify the best distribution of area overhead assigned to flip-flops and logic gates. The effectiveness of each of the proposed techniques is evaluated for a number of benchmark circuits. The experimental results reveal that our techniques provide satisfactory reliability gains and outperform the previously known approaches.
Download or read book Dissertation Abstracts International written by and published by . This book was released on 2006 with total page 862 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Design Analysis and Test of Logic Circuits Under Uncertainty written by Smita Krishnaswamy and published by Springer Science & Business Media. This book was released on 2012-09-21 with total page 130 pages. Available in PDF, EPUB and Kindle. Book excerpt: Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.
Download or read book Design for Yield and Reliability for Nanometer Cmos Digital Circuits written by Mostafa Hassan and published by LAP Lambert Academic Publishing. This book was released on 2014-01 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.
Download or read book Dynamic Threshold Technique for Soft Error Mitigation in Nanometer CMOS Circuits written by Nareshkumar Babulal Patel and published by . This book was released on 2010 with total page 128 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Mitigation of Thermally Induced Soft Errors in CMOS Nanoscale Circuits written by Md Sofikul Islam and published by . This book was released on 2017 with total page 212 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Analog IC Reliability in Nanometer CMOS written by Elie Maricau and published by Springer Science & Business Media. This book was released on 2013-01-11 with total page 208 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.
Download or read book VLSI written by Tomasz Wojcicki and published by CRC Press. This book was released on 2017-12-19 with total page 486 pages. Available in PDF, EPUB and Kindle. Book excerpt: Recently the world celebrated the 60th anniversary of the invention of the first transistor. The first integrated circuit (IC) was built a decade later, with the first microprocessor designed in the early 1970s. Today, ICs are a part of nearly every aspect of our daily lives. They help us live longer and more comfortably, and do more, faster. All this is possible because of the relentless search for new materials, circuit designs, and ideas happening on a daily basis at industrial and academic institutions around the globe. Showcasing the latest advances in very-large-scale integrated (VLSI) circuits, VLSI: Circuits for Emerging Applications provides a balanced view of industrial and academic developments beyond silicon and complementary metal–oxide–semiconductor (CMOS) technology. From quantum-dot cellular automata (QCA) to chips for cochlear implants, this must-have resource: Investigates the trend of combining multiple cores in a single chip to boost performance of the overall system Describes a novel approach to enable physically unclonable functions (PUFs) using intrinsic features of a VLSI chip Examines the VLSI implementations of major symmetric and asymmetric key cryptographic algorithms, hash functions, and digital signatures Discusses nonvolatile memories such as resistive random-access memory (Re-RAM), magneto-resistive RAM (MRAM), and floating-body RAM (FB-RAM) Explores organic transistors, soft errors, photonics, nanoelectromechanical (NEM) relays, reversible computation, bioinformatics, asynchronous logic, and more VLSI: Circuits for Emerging Applications presents cutting-edge research, design architectures, materials, and uses for VLSI circuits, offering valuable insight into the current state of the art of micro- and nanoelectronics.
Download or read book Soft Errors written by Jean-Luc Autran and published by CRC Press. This book was released on 2017-12-19 with total page 432 pages. Available in PDF, EPUB and Kindle. Book excerpt: Soft errors are a multifaceted issue at the crossroads of applied physics and engineering sciences. Soft errors are by nature multiscale and multiphysics problems that combine not only nuclear and semiconductor physics, material sciences, circuit design, and chip architecture and operation, but also cosmic-ray physics, natural radioactivity issues, particle detection, and related instrumentation. Soft Errors: From Particles to Circuits addresses the problem of soft errors in digital integrated circuits subjected to the terrestrial natural radiation environment—one of the most important primary limits for modern digital electronic reliability. Covering the fundamentals of soft errors as well as engineering considerations and technological aspects, this robust text: Discusses the basics of the natural radiation environment, particle interactions with matter, and soft-error mechanisms Details instrumentation developments in the fields of environment characterization, particle detection, and real-time and accelerated tests Describes the latest computational developments, modeling, and simulation strategies for the soft error-rate estimation in digital circuits Explores trends for future technological nodes and emerging devices Soft Errors: From Particles to Circuits presents the state of the art of this complex subject, providing comprehensive knowledge of the complete chain of the physics of soft errors. The book makes an ideal text for introductory graduate-level courses, offers academic researchers a specialized overview, and serves as a practical guide for semiconductor industry engineers or application engineers.
Download or read book Radiation Induced Soft Error written by Norbert Seifert and published by Now Publishers Inc. This book was released on 2010-11 with total page 136 pages. Available in PDF, EPUB and Kindle. Book excerpt: Radiation-induced Soft Errors: A Chip-level Modeling Perspective summarizes and discusses selected publications that enable a truly chip-level radiation-induced soft error rate estimation methodology.
