Download or read book Efficient Algorithms for Stochastic Decoding of LDPC Codes written by Kuo-Lun Huang and published by . This book was released on 2016 with total page 125 pages. Available in PDF, EPUB and Kindle. Book excerpt: The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models. We statistically analyze the behavior of stochastic LDPC decoding, including randomization in the stochastic streams and convergence of transition probabilities in iterative decoding process. We also present a space and time-efficient code bit determination method for stochastic LDPC decoders. In addition, we investigate and characterize the decoding errors of stochastic LDPC decoders and as an example, study the stochastic-decoding-specific trapping sets in the (1056,528) LDPC code used in the WiMAX standard. This study helps to develop methods to lower the error floor of stochastic decoding. We propose a reduced-latency stochastic decoding algorithm for LDPC codes. The proposed algorithm, called Conditional Stochastic Decoding (CSD), improves error rate performance and reduces the decoding latency by more than 30% compared with the existing stochastic decoders. We also characterize the performance of CSD in various communication schemes. For example, we show the advantages of using the proposed CSD algorithm in the Automatic Repeat reQuest (ARQ) scheme when compared with other iterative decoding algorithms. We extend our study of stochastic decoding to non-AWGN channel models including the Binary Symmetric Channel (BSC), the Z-channel, and the Rayleigh fading channel. We introduce scaling methods to improve the performance of stochastic decoding on these channel models. On the Rayleigh fading channel, the proposed method not only reduces the computational complexity of the stochastic decoding, but also provides 3-dB improvement in performance and lowers the error floor. Simplicity of hardware implementation, low latency, and good error rate performance of the proposed schemes make them suitable for emerging communication standards.

Download or read book Constructions Analyses and Decoding Algorithms of LDPC Codes and Error Control Codes for Flash Coding written by Qin Huang and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The fundamental problem in communication or storage systems is that of reproducing a message at another location or another time with high reliability. Channel codes or error control codes are the key techniques to guarantee reliable information transmission and storage. In the past six decades, many researchers dedicated themselves to design highly efficient error control codes. Low-density parity-check (LDPC) codes form a class of capacity-achievable codes with powerful soft-decision decoding algorithms. These decoding algorithms have linear complexity. Thus, many LDPC codes have been chosen as the standard codes for various next generations of communication systems and their applications to digital data storage systems are now being seriously considered and investigated. LDPC codes and efficient algorithms for decoding them form the most attractive topic in coding theory in the past 15 years. Two desirable structures for efficient hardware implementation of encoding and decoding of LDPC codes are cyclic and quasi-cyclic structures. In this dissertation, a new class of cyclic and a new class of quasi-cyclic LDPC codes are constructed by circulant decomposition. The new construction of cyclic LDPC codes enlarges the repertoire of cyclic codes constructed from finite geometries in 2000. Also presented in this dissertation are two simple but efficient novel reliability-based iterative decoding algorithms of LDPC codes. Both algorithms are devised based on the simple concepts of the one-step-majority-logic decoding algorithm. They provide efficient trade-offs between performance and decoding complexity. These two algorithms can be implemented in a single decoder with dual mode. In this dissertation, we also investigate application of error control codes to flash memories to reduce block erasures. Flash memories are the most promising devices to replace hard disk drives. However, block erasures are the most challenge problem for the life time of flash memories. Such operations are not only time-consuming, but also cause physical degradation and reduce the longevity of flash memories. A new efficient approach based on error control codes is proposed to reduce the frequency of block erasures.

Download or read book Stochastic Decoding of Low Density Parity check Codes written by Saeed Sharifi Tehrani and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book LDPC Codes on Finite Fields written by Juane Li and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Due to their capacity-approaching performance which can be achieved with practically implementable iterative decoding algorithms devised based on belief-propagation, low-density parity-check (LDPC) codes have rapid dominance in the applications requiring error control coding. This dissertation is intended to address certain important aspects of the aforementioned issues about LDPC codes. Subjects to be investigated include: (1) flexible and systematic methods for constructing binary LDPC codes with quasi-cyclic structure based on finite fields; (2) construction of high-rate and low-rate quasi-cyclic (QC) LDPC codes to achieve very low error rates without error-floor and with high rate of decoding convergence; (3) construction of binary QC-LDPC codes whose Tanner graphs have girth 8 or larger and contain minimum number of short cycles; (4) developing effective algorithms for enumerating short cycles in the Tanner graph of LDPC codes; (5) devising reduced-complexity decoding schemes and algorithms for binary QC-LDPC codes; (6) effective matrix-theoretic methods for constructing nonbinary (NB) LDPC codes; and (7) reduced-complexity decoding schemes and algorithms for NB LDPC codes. The dissertation presents a simple, flexible and systematic method to construct both binary and nonbinary LDPC codes with quasi-cyclic (QC) structure based on two arbitrary subsets of a finite field. One technique for constructing QC-LDPC codes whose Tanner graphs have girth 8 or larger is also proposed. Simulation results show that these constructed codes perform well over both the additive white Gaussian noise and the binary erasure channels. Also presented in this dissertation is a reduced-complexity decoding scheme to decode binary QC-LDPC codes. The decoding scheme is devised based on the section-wise cyclic structure of the parity-check matrix of a QC-LDPC code. The proposed decoding scheme combined with iterative decoding algorithms of LDPC codes results in no or a relative small performance degradation. Two efficient algorithms for enumerating short cycles in the Tanners graph of LDPC codes are presented. One algorithm is devised based on iterative message-passing algorithm by introducing messages in term of monomials, which is an improvement of the work of Karimi and Banihashemi. The other one is based on the trellis of an LDPC code by finding the partial paths which can form cycles. By removing certain number of cycles, a new code whose Tanner graph has a smaller number of short cycles, a larger girth, or both can be constructed. An algorithm to count and find cycles of lengths four and six in a class of QC-LDPC codes is also proposed. In this dissertation, we also briefly investigate one of the algebraic-based constructions of LDPC code, namely superposition (SP) construction, and one of the graph-based constructions, namely protograph-based (PTG-based) construction. The SP-construction method is re-interpreted in a broader scope from both the algebraic and the graph-theoretic perspectives. From the graph-theoretic point of view, it is shown that the PTG-based construction of LDPC codes is a special case of the SP-construction. An algebraic method for constructing PTG-based QC-LDPC codes through decomposing a small matrix is proposed. Several methods for constructing QC-LDPC codes through the SP-construction are also presented.

Download or read book Resource Efficient LDPC Decoders written by Vikram Arkalgud Chandrasetty and published by Academic Press. This book was released on 2017-12-05 with total page 192 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.The reader will learn: - Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation - How to reduce computational complexity and power consumption using computer aided design techniques - All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs - Provides extensive treatment of LDPC decoding algorithms and hardware implementations - Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware - Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis

Download or read book Turbo like Codes written by Aliazam Abbasfar and published by Springer Science & Business Media. This book was released on 2007-09-09 with total page 94 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps).

Download or read book Improved Coding Techniques for Digital Recording Systems written by Aman Bhatia and published by . This book was released on 2015 with total page 135 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation addresses various problems related to data encoding and error-correction techniques to design more reliable and higher density digital data storage technologies. In the second chapter, the problem of rewriting for multilevel flash memories is considered and a novel construction method for WOM codes based on lattices is proposed. Using the continuous approximation, hyperbolic write-regions are shown to be sum-rate optimal for arbitrary number of writes. An algorithm that determines an optimal encoding scheme is proposed for the case of two cells. Using these ideas, WOM codes are proposed that achieve high sum-rates. In the third chapter, the problem of designing a block-precoder for a magnetic recording channel is considered with the objective of minimizing the error rate. The precoder design problem is equivalent to solving a quadratic assignment problem which is NP-complete in general. Precoders are constructed using a branch-and-bound technique with a reduced search space, as well as using a sub-optimal local search algorithm. Simulation results show that these block-precoders out-perform existing precoding techniques. The fourth chapter discusses a novel technique for using polar codes for partial response channels. Multiple polar codes of various rates are designed for memoryless channels estimated by removing the effects of intersymbol interference from the partial response channel. Data is encoded using these codes and the codewords are interleaved before transmission. Decoding is done sequentially using a multi-stage decoding technique. Simulation results demonstrate that the performance of these codes is comparable to LDPC codes. The fifth chapter studies the performance of stochastic decoding on LDPC code ensembles in the limit of infinite blocklength. Two methods to perform the density evolution for stochastic decoding are provided. Alternative descriptions of the variable node update in stochastic decoding are given and connections to other decoding algorithms are highlighted. The sixth chapter explores the performance of binary images of non-binary LDPC codes. For the binary erasure channel, it is shown that the collection of stopping sets for a non-binary LDPC code are a subset of the collection of stopping sets of its basic binary image. An efficient algorithm is proposed that eliminates these additional stopping sets by adding redundant parity checks to the basic binary images. Simulation results confirm that the few redundant checks are sufficient to match the performance of the original non-binary LDPC codes with lower complexity.

Download or read book Area efficient Stochastic Decoder Architectures for Non binary LDPC Codes written by and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Relaxed Half stochastic Decoding Algorithm for LDPC Codes written by François Leduc-Primeau and published by . This book was released on 2009 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book High Speed Decoders for Polar Codes written by Pascal Giard and published by Springer. This book was released on 2017-08-30 with total page 108 pages. Available in PDF, EPUB and Kindle. Book excerpt: A new class of provably capacity achieving error-correction codes, polar codes are suitable for many problems, such as lossless and lossy source coding, problems with side information, multiple access channel, etc. The first comprehensive book on the implementation of decoders for polar codes, the authors take a tutorial approach to explain the practical decoder implementation challenges and trade-offs in either software or hardware. They also demonstrate new trade-offs in latency, throughput, and complexity in software implementations for high-performance computing and GPGPUs, and hardware implementations using custom processing elements, full-custom application-specific integrated circuits (ASICs), and field-programmable-gate arrays (FPGAs). Presenting a good overview of this research area and future directions, High-Speed Decoders for Polar Codes is perfect for any researcher or SDR practitioner looking into implementing efficient decoders for polar codes, as well as students and professors in a modern error correction class. As polar codes have been accepted to protect the control channel in the next-generation mobile communication standard (5G) developed by the 3GPP, the audience includes engineers who will have to implement decoders for such codes and hardware engineers designing the backbone of communication networks.

Download or read book Stochastic Decoding of LDPC Codes Over GF q written by Gabi Sarkis and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Low complexity High speed VLSI Design of Low density Parity check Decoders written by Zhiqiang Cui and published by . This book was released on 2008 with total page 218 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast convergence speed is highly desired in practice. This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We develop an efficient architecture for general permutation matrix based LDPC codes. We have explored various approaches to linearly increase the decoding throughput with a small amount of hardware overhead. We develop a multi-Gbit/sec LDPC decoder architecture for QC-LDPC codes and prototype an enhanced partially parallel decoder architecture for a Euclidian geometry based LDPC code on FPGA. We propose an early stopping scheme and an extended layered decoding method to reduce the number of decoding iterations for undecodable and decodable sequence received from channel. We also propose a low-complexity optimized 2-bit decoding approach which requires comparable implementation complexity to weighted bit flipping based algorithms but has much better decoding performance and faster convergence speed.

Download or read book Energy efficient Decoding of Low density Parity check Codes written by Kevin Cushon and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: "Low-density parity-check (LDPC) codes are a type of error correcting code that are frequently used in high-performance communications systems, due to their ability to approach the theoretical limits of error correction. However, their iterative soft-decision decoding algorithms suffer from high computational complexity, energy consumption, and auxiliary circuit implementation difficulties. It is of particular interest to develop energy-efficient LDPC decoders in order to decrease cost of operation, increase battery life in portable devices, lessen environmental impact, and increase the range of applications for these powerful codes.In this dissertation, we propose four new LDPC decoder designs with the primary goal of improving energy efficiency over previous designs. First, we present a bidirectional interleaver based on transmission gates, which reduces wiring complexity and associated parasitic energy losses. Second, we present an iterative decoder design based on pulse-width modulated min-sum (PWM-MS). We demonstrate that the pulse width message format reduces switching activity, computational complexity, and energy consumption compared to other recent LDPC decoder designs. Third, wepresent decoders based on differential binary (DB) algorithms. We also propose an improved differential binary (IDB) decoding algorithm, which greatly increases throughput and reduces energy consumption compared to recent decoders ofsimilar error correction capability. Finally, we present decoders based on gear-shift algorithms, which use multiple decoding rules to minimize energy consumption. We propose gear-shift pulse-width (GSP) and IDB with GSP (IGSP) algorithms, and demonstrate that they achieve superior energy efficiency without compromising error correction performance." --

Download or read book Optimizing and Decoding LDPC Codes with Graph based Techniques written by Amir H. Djahanshahi and published by . This book was released on 2010 with total page 117 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-density parity-check (LDPC) codes have been known for their outstanding error-correction capabilities. With low-complexity decoding algorithms and a near capacity performance, these codes are among the most promising forward error correction schemes. LDPC decoding algorithms are generally sub-optimal and their performance not only depends on the codes, but also on many other factors, such as the code representation. In particular, a given non-binary code can be associated with a number of different field or ring image codes. Additionally, each LDPC code can be described with many different Tanner graphs. Each of these different images and graphs can possibly lead to a different performance when used with iterative decoding algorithms. Consequently, in this dissertation we try to find better representations, i.e., graphs and images, for LDPC codes. We take the first step by analyzing LDPC codes over multiple-input single-output (MISO) channels. In an n_T by 1 MISO system with a modulation of alphabet size 2^M, each group of n_T transmitted symbols are combined and produce one received symbol at the receiver. As a result, we consider the LDPC-coded MISO system as an LDPC code over a 2^{M n_T}-ary alphabet. We introduce a modified Tanner graph to represent MISO-LDPC systems and merge the MISO symbol detection and binary LDPC decoding steps into a single message passing decoding algorithm. We present an efficient implementation for belief propagation decoding that significantly reduces the decoding complexity. With numerical simulations, we show that belief propagation decoding over modified graphs outperforms the conventional decoding algorithm for short length LDPC codes over unknown channels. Subsequently, we continue by studying images of non-binary LDPC codes. The high complexity of belief propagation decoding has been proven to be a detrimental factor for these codes. Thereby, we suggest employing lower complexity decoding algorithms over image codes instead. We introduce three classes of binary image codes for a given non-binary code, namely: basic, mixed, and extended binary image codes. We establish upper and lower bounds on the minimum distance of these binary image codes, and present two techniques to find binary image codes with better performance under belief propagation decoding algorithm. In particular, we present a greedy algorithm to find optimized binary image codes. We then proceed by investigation of the ring image codes. Specifically, we introduce matrix-ring-image codes for a given non-binary code. We derive a belief propagation decoding algorithm for these codes, and with numerical simulations, we demonstrate that the low-complexity belief propagation decoding of optimized image codes has a performance very close to the high complexity BP decoding of the original non-binary code. Finally, in a separate study, we investigate the performance of iterative decoders over binary erasure channels. In particular, we present a novel approach to evaluate the inherent unequal error protection properties of irregular LDPC codes over binary erasure channels. Exploiting the finite length scaling methodology, that has been used to study the average bit error rate of finite-length LDPC codes, we introduce a scaling approach to approximate the bit erasure rates in the waterfall region of variable nodes with different degrees. Comparing the bit erasure rates obtained from Monte Carlo simulation with the proposed scaling approximations, we demonstrate that the scaling approach provides a close approximation for a wide range of code lengths. In view of the complexity associated with the numerical evaluation of the scaling approximation, we also derive simpler upper and lower bounds and demonstrate through numerical simulations that these bounds are very close to the scaling approximation.

Download or read book High Performance and Energy Efficient Decoder Design for Non Binary LDPC Codes written by Yuta Toriyama and published by . This book was released on 2016 with total page 133 pages. Available in PDF, EPUB and Kindle. Book excerpt: Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts. Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency. We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.

Download or read book Channel Coding Theory Algorithms and Applications written by and published by Academic Press. This book was released on 2014-07-29 with total page 687 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book gives a review of the principles, methods and techniques of important and emerging research topics and technologies in Channel Coding, including theory, algorithms, and applications. Edited by leading people in the field who, through their reputation, have been able to commission experts to write on a particular topic. With this reference source you will: - Quickly grasp a new area of research - Understand the underlying principles of a topic and its applications - Ascertain how a topic relates to other areas and learn of the research issues yet to be resolved - Quick tutorial reviews of important and emerging topics of research in Channel Coding - Presents core principles in Channel Coding theory and shows their applications - Reference content on core principles, technologies, algorithms and applications - Comprehensive references to journal articles and other literature on which to build further, more specific and detailed knowledge

Download or read book Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory written by Kasra Vakilinia and published by . This book was released on 2016 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation mainly focuses on two different branches of coding theory and its applications:1) coding to approach capacity in short blocklengths using feedback and 2) LDPC coding for Flash memory systems. In the first area, we study the benefits that feedback with incremental redundancy can provide to increase the maximum achievable rate in communication systems, using carefully designed adaptive non-binary LDPC codes. We show how to achieve over 90% of the idealized throughput of rate-compatible sphere-packing with maximum-likelihood decoding (RCSP-ML) for average blocklengths of 150-450 bits. This is important because it illustrates that feedback greatly reduces the number of transmitted symbols required to achieve near-capacity performance. We then extend these ideas to feedback systems where the number of incremental transmissions is limited. In order to optimize the blocklengths for each incremental transmission we formulate an integer optimization problem involving an approximation based on the inverse-Gaussian p.d.f., the distribution of the blocklength required for successful decoding. The brute-force approach to solve this computationally complex optimization problem quickly becomes infeasible. In order to solve this problem efficiently, we introduce sequential differential optimization (SDO) algorithm that has only linear complexity to identify optimal incremental transmission lengths. The results obtained from SDO are negligibly different from the exponentially complex exhaustive-search solution. By using the optimized incremental transmission lengths (with an average blocklength of less than 500 bits), non-binary LDPC codes achieve a throughput greater than 90% of the capacity with a two-phase scheme. Furthermore, we extend these ideas to the case of using cyclic redundancy checks (CRC). With CRC, even better performance in the blocklength range of about 500 bits is obtainable. The overhead associated with a CRC prevents great performance in short blocklength regime (fewer than 400 bits). We also extend these ideas to systems with larger constellations operating at a higher signal-to-noise ratio (SNR). Another incremental transmission coding scheme studied in this dissertation focuses on de- sign and use of rate-compatible protograph-based raptor-like (PBRL) LDPC codes with various blocklengths and rates that can be used in feedback systems over additive-white Gaussian noise (AWGN) channels. The codes proposed in this work use X-OR operations and density evolution to produce additional degree-one parity bits providing extensive rate compatibility. The protographs are also carefully lifted to avoid undesirable graphical structures such as problematic stopping sets. For a target frame error rate of 10 5, at each rate the k = 1032 and k = 16384 code families perform within 1 dB and 0.4 dB, respectively, of both the Gallager bound and the normal approximation. The k = 16384 code family outperforms the best known standardized code family, the AR4JA and longer DVB-S2 codes. We extend the ideas in design of PBRL codes from AWGN channels to binary symmetric channels (BSC) and binary erasure channels (BEC). We introduce two fast and efficient algorithms to calculate the threshold of LDPC codes used over BSC. These algorithms serve as alternatives to the quite complex density evolution algorithm. Since these new algorithms are quite fast, we use them to design PBRL LDPC codes for BSC. To explore the advantage of feedback in conjunction with other modern coding schemes, in this work we use an extension of reciprocal channel approximation (RCA) to accurately and effi- ciently predict the frame error rate (FER) performance of polar codes by analyzing the probability density function (p.d.f.) of the log-likelihood ratio (LLR) values associated with information bits. The preliminary results show that a feedback scheme in conjunction with a repetition coding sys- tem significantly reduces the blocklength required to achieve a target FER. For example, using a rate-0.5 128-bit polar code as the initially transmitted code, the theoretical analysis verified by simulation shows a 16-fold reduction in blocklength with only about 7.4% of overhead in forward channel transmissions. We also make an improvement to this feedback coding scheme which reduces the overhead to almost 3% for a similar FER performance gain. The second part of this dissertation focuses on design of binary and non-binary LDPC codes for Flash memory systems. Usually the FER requirements in Flash memory systems is more strict than wireless communication systems. In order to improve the error correction capability of the codes used in Flash memory systems, sometimes the same memory cell is read multiple times. In this dissertation, we study the coding gain from multiple reads of the same Flash memory cell with distinct word-line voltages. The subsequent additional reads provide enhanced precision for LDPC decoding. We identify a trade-off in LDPC code design when decoding is performed with multiple precision levels and conclude that the best code at one level of precision is typically not be the best code at a different level of precision. By studying the trade-off in LDPC code design by using extrinsic-information-transfer (EXIT)- function analysis employing the reciprocal channel approximation (RCA), we obtain the optimal LDPC code degree distributions for initial hard decoding (one-bit quantization of the channel out- put) and for decoding with the soft information provided by subsequent additional reads in both SLC (two-level cell) and MLC (four-level-cell) Flash memory. The results indicate that design for hard decoding can provide irregular degree distributions that have good thresholds across a range of possible decoding precisions. Finally, we illustrate that the MMI optimization of word-line voltages for five reads is a quasi-convex problem for the Gaussian model of SLC Flash.