Download or read book Design and characterization of transmitter circuits architectures using silicon ring resonator modulators for high bit rate communications written by Olivier Dubray and published by . This book was released on 2017 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt: Over the past decade, with the diversification of connected devices (PCs, Tablets, TVs and Smartphones), the Internet ecosystem has drastically extended. Today, 80 % world traffic is concentrated in the data centers where the data rate, the size and the cost is still growing. To address such scaling issues as bandwidth density, energy consumption and cost of the interconnects inside the data centers, the development of new optical transmitters is critical. The aim of this thesis is to propose and evaluate transmitter architectures using silicon photonics technology to address next 400 Gbit/s data rate standard over up to 2 kilometer links. The selected electro-optical modulator is the silicon ring resonator modulator which has substantial benefits: low footprint, low energy consumption and enables dense multiplexing. The optical transmitter architectures evaluations were successively optimized: from the active junction to the complete optical transmitter. This study identified the performances trade-offs impacted by the ring resonator modulator parameters. A compact model was generated to physically optimize the component in a reduced simulation time. Then, using the compact model, two transmitter architectures were studied based on classical architecture. Both are based on eight ring resonator modulators arranged in series modulating eight different wavelengths. The difference is the modulation format: the first one is electrically modulated at 50 Gbaud in 2-levels pulse amplitude modulation (PAM-2) and the second one at 25 Gbaud 4-levels pulse amplitude modulation (PAM-4). The two solutions fit the 400 Gbit/s performances demand with the use of the same trade-offs. Finally, new transmitter architectures were proposed to generate PAM-4 modulation. Unlike the previous architecture, they have in input two parallel bit streams which are optically combined to generate the PAM-4 modulation. The first solution is based on two silicon ring resonator modulator arranged in series. This architecture was validated through 30 Gbit/s transmission characterizations with only 1 Vpp. A second solution was then proposed, based on two silicon ring resonator modulators arranged in parallel in a Mach Zehnder interferometer. In the same way, transmission characterizations at 30 Gbit/s with 1.2 Vpp allows this architecture to be validated.
Download or read book Design and Characterization of 35 GHz Silicon Photonic Travelling Wave Modulator for Next Generation Short Reach Communication Links written by Alireza Samani and published by . This book was released on 2015 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: "The ever increasing internet traffic driven by the constant spread of cloud services offered by data centers and the increasing demand for higher bandwidth driven by web-based media applications and services have increased the need for faster and inexpensive short reach optic solutions. With the commercialization and deployment of 100 Gb/s technologies, and the development of 400 Gb/s systems, there is a clear need for inexpensive and power efficient building blocks. Currently 100 Gb/s transmission of Ethernet frames over single mode fiber (SMF) is realized using a four color wavelength division multiplexing (WDM) setting in a 4 × 25 Gb/s format. However, it is widely agreed that the 400 Gb/s systems will be realized using 4 × 100 Gb/s configuration, which necessitates the need for a single wavelength operation at 100 Gb/s. To achieve higher data rate transmission, advance optical modulation formats together with polarization and wavelength division multiplexing are required. Pulse amplitude modulation (PAM) enables higher spectral efficiency by using multi-level amplitudes. Using PAM-4 modulation format doubles the spectral efficiency of the optical link. Recently PAM generation has been demonstrated using Silicon Photonics (SiP) intensity modulators. In this thesis, we present a 4.2 mm long, 35 GHz bandwidth single drive series push pull silicon travelling wave Mach-Zehnder modulator (TW-MZM) based on lateral PN junction operating near 1550 nm wavelength. A bit-rate of 112 Gb/s is achieved using PAM-4 modulation scheme at 56 Gbaud after 2 km of single mode fiber (SMF) below the hard decision pre forward error correction (Pre-FEC) threshold of 3.8 × 10-3 to provide a final bit error rate under 10-15. To the best of our knowledge this modulator surpasses the highest bandwidth reported for a SiP modulator by 5 GHz. " --
Download or read book Silicon Based RF Front Ends for Ultra Wideband Radios written by Aminghasem Safarian and published by Springer. This book was released on 2009-09-03 with total page 97 pages. Available in PDF, EPUB and Kindle. Book excerpt: A comprehensive study of silicon-based distributed architectures in wideband circuits are presented in this book. Novel circuit architectures for ultra-wideband (UWB) wireless technologies are described. The book begins with an introduction of several transceiver architectures for UWB. The discussion then focuses on RF front-end of the UWB radio. Therefore, the book will be of interest to RF circuit designers and students.
Download or read book Digitally Assisted Fully Integrated Wideband Transmitters for High Speed Millimeter Wave Wireless Communication Links written by David del Rio and published by Springer. This book was released on 2018-07-07 with total page 269 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents design methods and considerations for digitally-assisted wideband millimeter-wave transmitters. It addresses comprehensively both RF design and digital implementation simultaneously, in order to design energy- and cost-efficient high-performance transmitters for mm-wave high-speed communications. It covers the complete design flow, from link budget assessment to the transistor-level design of different RF front-end blocks, such as mixers and power amplifiers, presenting different alternatives and discussing the existing trade-offs. The authors also analyze the effect of the imperfections of these blocks in the overall performance, while describing techniques to correct and compensate for them digitally. Well-known techniques are revisited, and some new ones are described, giving examples of their applications and proving them in real integrated circuits.
Download or read book Design of Digital centric Polar Modulation Transmitters for High data rate Communications written by Ioannis Loukas Syllaios and published by . This book was released on 2010 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: A novel baseband complex-envelope is proposed for the analysis and characterization of polar modulators. It is composed of single-tone envelope and phase signals and it provides a solid foundation for the accurate analysis of polar modulators using the low-pass equivalent model, previously described. Closed form expressions are derived that clearly identify the aforementioned sources of distortion on the reconstructed discrete-time baseband complex-envelope. Using these expressions, the optimal design requirements of the envelope modulator and/or the phase modulator are investigated that lead to minimally distorted complex-modulated RF carrier.
Download or read book Top Down Design of High Performance Sigma Delta Modulators written by Fernando Medeiro and published by Springer Science & Business Media. This book was released on 2013-04-18 with total page 303 pages. Available in PDF, EPUB and Kindle. Book excerpt: The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.
Download or read book Transceiver and System Design for Digital Communications written by Scott R. Bullock and published by SciTech Publishing. This book was released on 2000 with total page 282 pages. Available in PDF, EPUB and Kindle. Book excerpt: This system-level approach to transceiver design covers digital communications principles for military applications and translating those concepts for commercial applications. Topics include link budget, receiver and transmitter specifications, modulation, and spread spectrum.
Download or read book Design of High speed Communication Circuits written by Ramesh Harjani and published by World Scientific. This book was released on 2006 with total page 233 pages. Available in PDF, EPUB and Kindle. Book excerpt: MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible. The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O. Contents: Achieving Analog Accuracy in Nanometer CMOS (M P Flynn et al.); Self-Induced Noise in Integrated Circuits (R Gharpurey & S Naraghi); High-Speed Oversampling Analog-to-Digital Converters (A Gharbiya et al.); Designing LC VCOs Using Capacitive Degeneration Techniques (B Jung & R Harjani); Fully Integrated Frequency Synthesizers: A Tutorial (S T Moon et al.); Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits (D J Allstot et al.); Equalizers for High-Speed Serial Links (P K Hanumolu et al.); Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation (C P Yue et al.). Readership: Technologists, scientists, and engineers in the field of high-speed communication circuits. It can also be used as a textbook for graduate and advanced undergraduate courses.
Download or read book Fibre Optic Communication Devices written by Norbert Grote and published by Springer Science & Business Media. This book was released on 2001-01-26 with total page 496 pages. Available in PDF, EPUB and Kindle. Book excerpt: Optoelectronic devices and fibre optics are the basis of cutting-edge communication systems. This monograph deals with the various components of these systems, including lasers, amplifiers, modulators, converters, filters, sensors, and more.
Download or read book Charge based CMOS Digital RF Transmitters written by Pedro Emiliano Paro Filho and published by Springer. This book was released on 2016-09-27 with total page 180 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces a completely novel architecture that can relax the trade-off existing today between noise, power and area consumption in a very suitable solution for advanced wireless communication systems. Through the combination of charge-domain operation with incremental signaling, this architecture gives the best of both worlds, providing the reduced area and high portability of digital-intensive architectures with an improved out-of-band noise performance given by intrinsic noise filtering capabilities. Readers will be enabled to design higher performance radio front-ends that consume less power and area, especially with respect to the transmitter and power amplifier designs, considered by many the “battery killers” on most mobile devices.
Download or read book High Data Rate Transmitter Circuits written by C.J. de Ranter and published by Springer. This book was released on 2010-12-07 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This practical guide and introduction to the design of key RF building blocks used in high data rate transmitters emphasizes CMOS circuit techniques applicable to oscillators and upconvertors. The book is written in an easily accessible manner, without losing detail on the technical side.
Download or read book Energy efficient Wideband Transceiver Architectures and Circuits for High speed Communications and Interconnects written by Jianyun Hu and published by . This book was released on 2012 with total page 170 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Recently with the increasing demand for high-speed communications, wideband systems have becomes one of the major research focuses for both academia and industry. While wide bandwidth benefits high data-rate communication, compared to the conventional narrow bandwidth system, it poses large design challenges for both transceiver architectures and circuits, especially using the mainstream low cost CMOS and BiCMOS technologies. Besides, wideband systems typically inevitably require large power consumption, which might lead to worse energy-efficiency compared to the narrow-band systems. Therefore, in this thesis, we will focus on the energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects: ultra-wideband impulse radios (IR-UWB), intra-chip free-space optical interconnect, and on-chip electrical interconnect for multi-core processors. Ultra-wideband communications has become an active research topic with the approval of UWB technology for commercial applications in the 3.1 - 10.6-GHz band by FCC. With such a large bandwidth, UWB technologies promise to offer low-power and high-speed wireless connectivity for future short-range communication systems. In this thesis, we will focus on the energy-efficient, wide-band UWB receiver architecture and circuits. We will first present a new UWB low-noise amplifier with noise cancelation, and use it to investigate the design trade-off for UWB amplifier. Then we will present a new analog correlation receiver architecture. It employs an energy-efficient correlator called distributed pulse correlator (DPC) for low power ultra-wideband pulse detection. Thanks to the multiple pulsed multipliers time-interleaved in a distributed fashion and built-in local template pulse generation in the DPC, the power consumption and circuit complexity are significantly reduced for the DPC-based analog correlation receiver. The operation and performance of the DPC are analyzed, and the circuit implementation of DPC is discussed in details, especially the most critical component, the pulsed multiplier. A chip prototype of the DPC-based IR-UWB receiver was implemented in a 0.18-[mu]m standard digital CMOS technology. In the measurement, the 8-tap, 10-GSample/s DPC achieves a pulse rate of 250 MHz with an energy efficiency of 40 pJ/pulse, and the whole receiver achieves an energy efficiency of 190 pJ/pulse at the 250-MHz pulse rate. Together with a UWB transmitter and two UWB antennas, the complete IR-UWB communication link is also demonstrated. The continuous scaling of CMOS technology enables more and more modules to be implemented into a single chip. However, it actually poses challenges in the global interconnect design, especially with the rapid demand for higher-speed communication among more modules. Conventional electrical interconnect inevitably requires significant improvement for this high-speed on-chip global communication. In this thesis, we will investigate the high-speed global interconnect through both electrical and optical options. Optical interconnects have been recognized as a promising successor to electrical interconnects. They have advantages like large bandwidth, low latency, and less susceptible to noise. We will present a novel optical transceiver architecture and circuits for the free-space optical interconnect for high-speed intra-chip communications. Compared to the conventional embedded-clock and forwarded-clock architectures, the presented shared-clock architecture benefits low power and low design complexity on the clock generation and recovery block and a simple interface between electrics and optics. An injection-locked oscillator is employed to replace the conventional phase-locked loop as the clock generation block to further improve the energy-efficiency. Due to the high-speed and large bandwidth requirement, bandwidth extension techniques are widely used in the transceiver circuits. The optical transceiver was implemented in a 0.13-[mu]m standard digital CMOS technology. The simulation results show that a 10-Gb/s data rate with 7.1-pJ/b energy-efficiency communication can be achieved. For the electrical interconnect, we will present a novel on-chip interconnect system for multi-core chips using transmission lines as shared media in this thesis. It supports both point-to-point and broadcasting communications. Compared to network-on-chip approaches, it offers significant advantages in circuit complexity, energy efficiency and link latency. To demonstrate the scheme, a chip prototype with two 20-mm transmission lines running in parallel and multiple transmitters/receivers (including 2:1 serializer/1:2 deserializer) was implemented in a 130-nm SiGe BiCMOS technology. The transmission lines are designed with Ground-Signal-Signal-Ground configuration and patterned ground shields to exhibit low latency, small attenuation, generate less crosstalk, and provide high bandwidth density. The transceivers are designed and optimized to achieve good energy efficiency at the target data rate of 25 Gb/s. On the transmitter side, an efficient and low power pre-emphasis technique is applied to compensate for the transmission line's frequency-dependent loss. On the receiver side, latched samplers are adopted for high sensitivity. To eliminate the insertion loss caused by a dedicated isolation switch, both the transmitter and receiver are designed to be internally switched in/out from the transmission lines. The prototype can successfully demonstrate point-to-point and broadcasting communications, and can achieve a date rate of 25.4 Gb/s with an energy efficiency of 1.67 pJ/b in the measurement"--Pages v-vii.
Download or read book Design and Analysis of Digitally Modulated Transmitters for Efficiency Enhancement written by LU. YE and published by . This book was released on 2013 with total page 288 pages. Available in PDF, EPUB and Kindle. Book excerpt: The last decade has witnessed a tremendous growth in wireless communications. Consumer demands for battery-operated mobile devices with versatile, high data-rate communication capabilities that are of low cost, small form-factor and long operating cycle have motivated the research on fully-integrated, back-off-efficient and coexistence-friendly wireless transceivers in CMOS VLSI technology. However, the full integration of an efficient CMOS power amplifier (PA) into such a transceiver is still among the most difficult challenges towards a true System-On-Chip (SOC) solution. This thesis investigates the PA efficiency enhancement techniques for a complete power transmitter system that is fully-integrated and coexistable. Direct digitally modulated transmitter architecture has been identified as one of the most promising solutions to the above challenges. Within such a transmitter, the PA efficiency is able to back off from a high peak efficiency at least with class-B characteristic; meanwhile, the transmit linearity can be more easily improved by digital predistortion due to the direct digital modulation scheme. To validate such a promising architecture, we have built a fully-integrated CMOS digital power transmitter for the IEEE 802.11g 54Mbps application. System-level considerations and design choices are presented with an aim for low out-of-band noise and good transmit linearity. As the core of the transmitter, the RF switching PA is designed for high efficiency with minimum number of on-chip passives that only exercise an accurate control over fundamental and second-harmonic terminations. The class-B efficiency back-off characteristic is further improved by a dynamic impedance modulator which boosts the PA drain impedance at a low instantaneous envelope level. Open-loop phase interpolator based topology is used for the polar phase modulator, which achieves wideband phase modulation with competitive power consumption. Digital baseband filtering is fully optimized at both the algorithm and the hardware level, which offers larger than 60dB attenuation on the close-in spectral images with reduced filter complexity. The prototype has been implemented in a 65nm bulk CMOS technology and has demonstrated a combination of good output power, overall efficiency and spectral purity with a very high level of system integration.
Download or read book Analog Baseband Architectures and Circuits for Multistandard and Low Voltage Wireless Transceivers written by Pui-In Mak and published by Springer. This book was released on 2010-11-20 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents architectural and circuit techniques for wireless transceivers to achieve multistandard and low-voltage compliance. It provides an up-to-date survey and detailed study of the state-of-the-art transceivers for modern single- and multi-purpose wireless communication systems. The book includes comprehensive analysis and design of multimode reconfigurable receivers and transmitters for an efficient multistandard compliance.
Download or read book Transmitter Systems and Bidirectional RF Front End for Millimeter Wave Communications written by Po-Yi Wu and published by . This book was released on 2015 with total page 135 pages. Available in PDF, EPUB and Kindle. Book excerpt: In this dissertation, millimeter-wave transmitter systems and a bidirectional transceiver front-end circuit are presented. To reach high data rate for next generation communication systems, complex modulation schemes such as QAM are necessary to take advantage of the signal bandwidth. In a transmitter system, higher-order QAM not only requires the PA to operate in linear region, while the output power and efficiency are maintained, but also requires the calibrations for the modulator to minimize the EVM. The rst portion of the dissertation presents the dual-band (Q-band/W-band) direct-conversion transmitter in 120-nm SiGe BiCMOS process. The dual-band feature is the use of the proposed transmission- line-based dual-band load on RF and LO amplifiers to allow the transmitter to operate at two distinct bands. Furthermore, this dual-band transmitter applies a new I/Q correction techniques, which calibrates amplitude and phase mismatch from analog baseband, and can achieve the sideband suppression ratio above 40 dBc at both Q-band and W-band. The EVM improvement can be clearly found from the constellation diagram at both bands. In addition, a high-efficiency PA must introduce nonlinear terms and degrade the EVM. Therefore, in addition to the I/Q mismatch, other errors from a transmitter such as LO leakage, AM-AM, AM-PM distortion and memory effects must be calibrated to improve the EVM. The second portion of this dissertation discusses the demonstrations of 45-GHz and 94-GHz transmitter systems with digital predistortion (DPD) to compromise the linearity/efficiency trade-off. The 45-GHz transmitter system uses the second portion SiGe modulator and a two-by-two PA/antenna array, which PAs are implemented in 45-nm SOI CMOS process. The digital signal is programmed in an FPGA-based processor, so an all silicon-based solution is verified at 45 GHz (Q-band). The 94-GHz transmitter system uses a two-step frequency conversion architecture to send the modulated data to 94-GHz band and a two-by-four PA/antenna array, which is implemented in 45-nm SOI CMOS process. The nonlinearities and errors of the transmitted data are significantly predistorted/calibrated and the EVM is greatly improved by DPD. The third portion of this dissertation presents a 71 to 86-GHz (E-band) bidirectional transceiver front-end circuit implemented in 90-nm SiGe BiCMOS process. The time-division duplex architecture avoids transmit/receive switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a novel PA/LNA circuit, which alleviates the parasitic loading of each circuit. In transmit mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In receive mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz.
Download or read book Architectures for Baseband Signal Processing written by Frank Kienle and published by Springer. This book was released on 2013-08-13 with total page 260 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book addresses challenges faced by both the algorithm designer and the chip designer, who need to deal with the ongoing increase of algorithmic complexity and required data throughput for today’s mobile applications. The focus is on implementation aspects and implementation constraints of individual components that are needed in transceivers for current standards, such as UMTS, LTE, WiMAX and DVB-S2. The application domain is the so called outer receiver, which comprises the channel coding, interleaving stages, modulator, and multiple antenna transmission. Throughout the book, the focus is on advanced algorithms that are actually in use in modern communications systems. Their basic principles are always derived with a focus on the resulting communications and implementation performance. As a result, this book serves as a valuable reference for two, typically disparate audiences in communication systems and hardware design.
Download or read book Top Down Design of High Performance Sigma Delta Modulators written by Fernando Medeiro and published by Springer. This book was released on 2013-01-11 with total page 287 pages. Available in PDF, EPUB and Kindle. Book excerpt: The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.
