Download or read book Concurrent Error Detection in Self timed VLSI written by David A. Rennels and published by . This book was released on 1993 with total page 20 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from DCVSL self-timed logic are compared with a checker that is composed of a tree of dual-rail (morphic) comparators to detect errors and signal completion. An efficient implementation is shown that compares favorably in speed and area with conventional completion signal generators. The control of the pipeline is then examined, and techniques are described that detect errors in the C-gates and other circuits that provide handshaking control. Based on these studies we have concluded that self- timed logic offers considerable fault-tolerance potential due to its built- in redundancy that can be effectively exploited for error checking."
Download or read book Concurrent Error Detection in VLSI Systems Through Structure Encoding written by Wesley Kent Fuchs and published by . This book was released on 1985 with total page 154 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book On Line Testing for VLSI written by Michael Nicolaidis and published by Springer Science & Business Media. This book was released on 2013-03-09 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.
Download or read book On Concurrent Error Detection in VLSI Array Structures written by Ravi Kumar Gulati and published by . This book was released on 1985 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book FTCS 24 written by and published by . This book was released on 1994 with total page 496 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Development of a VLSI Processor Incorporating Hardware Concurrent Error Detection and Correction written by Ian David Elliott and published by . This book was released on 1990 with total page 288 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Foundations of Dependable Computing written by Gary M. Koob and published by Springer Science & Business Media. This book was released on 2007-08-19 with total page 325 pages. Available in PDF, EPUB and Kindle. Book excerpt: Foundations of Dependable Computing: System Implementation, explores the system infrastructure needed to support the various paradigms of Paradigms for Dependable Applications. Approaches to implementing support mechanisms and to incorporating additional appropriate levels of fault detection and fault tolerance at the processor, network, and operating system level are presented. A primary concern at these levels is balancing cost and performance against coverage and overall dependability. As these chapters demonstrate, low overhead, practical solutions are attainable and not necessarily incompatible with performance considerations. The section on innovative compiler support, in particular, demonstrates how the benefits of application specificity may be obtained while reducing hardware cost and run-time overhead. A companion to this volume (published by Kluwer) subtitled Models and Frameworks for Dependable Systems presents two comprehensive frameworks for reasoning about system dependability, thereby establishing a context for understanding the roles played by specific approaches presented in this book's two companion volumes. It then explores the range of models and analysis methods necessary to design, validate and analyze dependable systems. Another companion to this book (published by Kluwer), subtitled Paradigms for Dependable Applications, presents a variety of specific approaches to achieving dependability at the application level. Driven by the higher level fault models of Models and Frameworks for Dependable Systems, and built on the lower level abstractions implemented in a third companion book subtitled System Implementation, these approaches demonstrate how dependability may be tuned to the requirements of an application, the fault environment, and the characteristics of the target platform. Three classes of paradigms are considered: protocol-based paradigms for distributed applications, algorithm-based paradigms for parallel applications, and approaches to exploiting application semantics in embedded real-time control systems.
Download or read book Asynchronous On Chip Networks and Fault Tolerant Techniques written by Wei Song and published by CRC Press. This book was released on 2022-05-10 with total page 302 pages. Available in PDF, EPUB and Kindle. Book excerpt: Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications. As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts – faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks. This book will serve as an essential guide for researchers and students studying interconnection networks, fault-tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.
Download or read book Defect and Fault Tolerance in VLSI Systems written by Israel Koren and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 362 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.
Download or read book A Concurrent Error Detection and Correction Algorithm for Fault tolerant VLSI Arithmetic Array Processors written by Kamran Shokoohi-Kayvan and published by . This book was released on 1985 with total page 284 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Proceedings written by and published by . This book was released on 2005 with total page 624 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Application of Time Redundancy to Concurrent Error Detection in VSLI Circuits written by Haytham H. Hana and published by . This book was released on 1987 with total page 192 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Fehlertolerierende Rechensysteme Fault Tolerant Computing Systems written by Fevzi Belli and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 401 pages. Available in PDF, EPUB and Kindle. Book excerpt: Dieser Band enthält die 38 Beiträge der 3. GI/ITG/GMA-Fachtagung über "Fehlertolerierende Rechensysteme". Unter den 10 aus dem Ausland eingegangenen Beiträgen sind 4 eingeladene Vorträge. Insgesamt dokumentiert dieser Tagungsband die Entwicklung der Konzeption und Implementierung fehlertoleranter Systeme in den letzten drei Jahren vor allem in Europa. Sämtliche Beiträge sind neue Forschungs- oder Entwicklungsergebnisse, die vom Programmausschuß der Tagung aus 70 eingereichten Beiträgen ausgewählt wurden.
Download or read book Asian Test Symposium written by and published by . This book was released on 2004 with total page 504 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Dependable Computing EDCC 2 written by Andrzej Hlawiczka and published by Springer Science & Business Media. This book was released on 1996-09-18 with total page 468 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the Second European Dependable Computing Conference, EDCC-2, held in Taormina, Italy, in October 1996. The book presents 26 revised full papers selected from a total of 66 submissions based on the reviews of 146 referees. The papers are organized in sections on distributed fault tolerance, fault injection, modelling and evaluation, fault-tolerant design, basic hardware models, testing, verification, replication and distribution, and system level diagnosis.
Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1995 with total page 602 pages. Available in PDF, EPUB and Kindle. Book excerpt: Lists citations with abstracts for aerospace related reports obtained from world wide sources and announces documents that have recently been entered into the NASA Scientific and Technical Information Database.
Download or read book 11th Asian Test Symposium ATS 02 written by and published by IEEE Computer Society Press. This book was released on 2002 with total page 464 pages. Available in PDF, EPUB and Kindle. Book excerpt: Held in Guam in November of 2002, the symposium on the test technologies and research issues related to silicon chip production, resulted in the 74 papers presented here. The papers are organized into sections related to the symposium sessions on test generation, on-line testing, analog and mixed si
