Download or read book Concurrent Error Detection in Arithmetic and Logic Units written by Leona Yuk-Ye Fung and published by . This book was released on 1982 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Concurrent Error Detection written by Steven Scott Gorshe and published by . This book was released on 2002 with total page 246 pages. Available in PDF, EPUB and Kindle. Book excerpt: Concurrent error detection (CED) is the detection of errors or faults in a circuit or data path concurrent with normal operation of that circuit. The general approach for CED is to calculate a check symbol for the inputs to the circuit under operation, predict the check symbol that will result for the output of the circuit for those inputs, and compare the predicted check symbol to the one that is actually calculated for the output. If the predicted and actual check symbols are different, an error or fault has been detected. The alternative to this check symbol prediction is to use a second copy of the circuit under operation and compare the results of the two circuits. For some classes of circuits the prediction of the output check symbol can require less circuitry than a second copy of the circuit being tested. Four examples of these types of circuits are examined in this dissertation: Arithmetic Logic Units (ALUs), array multipliers, self-synchronous scrambler-descrambler pairs with their intervening data path, and switch fabrics. Faults in integrated circuits tend to produce unidirectional errors. Unidirectional errors are those in which all of the errors are in the same direction (e.g., 0 to 1 errors) within the block of data covered by a given check symbol. For this reason, codes that are optimized for unidirectional errors are the focus of investigation for most of the applications. In particular, the Bose-Lin codes are examined for those applications where unidirectional errors are expected to be typical. In order to examine the performance of the Bose-Lin codes in one of these applications, it was necessary to determine the theoretical performance for Bose- Lin codes for error rates beyond what had been previously studied. This analysis of Bose-Lin codes with large numbers of "burst" errors also included a further generalization of the codes.
Download or read book Concurrent Error detecting Codes for Arithmetic Processors written by Raymond S. Lim and published by . This book was released on 1979 with total page 36 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Concurrent Error Detecting Codes for Arithmetic Processors written by National Aeronautics and Space Administration (NASA) and published by Createspace Independent Publishing Platform. This book was released on 2018-07-25 with total page 28 pages. Available in PDF, EPUB and Kindle. Book excerpt: A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes. Lim, R. S. Ames Research Center NASA-TP-1528, A-7810 RTOP 366-18-50-00-00
Download or read book Concurrent Error Detection in Arithmetic Processors Using absolute Value Of G3N subscript M Codes written by James Lawrence Olivier and published by . This book was released on 1988 with total page 324 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book A Concurrent Error Detection and Correction Algorithm for Fault tolerant VLSI Arithmetic Array Processors written by Kamran Shokoohi-Kayvan and published by . This book was released on 1985 with total page 284 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Concurrent Error Detection in Finite Field Arithmetic Operations written by Siavash Bayat-Sarmadi and published by . This book was released on 2008 with total page 175 pages. Available in PDF, EPUB and Kindle. Book excerpt: With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults specially in sensitive and critical applications may cause serious failures and hence should be avoided. On the other hand, some critical applications such as cryptosystems may also be prone to deliberately injected faults by malicious attackers. Some of these faults can produce erroneous results that can reveal some important secret information of the cryptosystems. Furthermore, yield factor improvement is always an important issue in VLSI design and fabrication processes. Digital systems such as cryptosystems and digital signal processors usually contain finite field operations. Therefore, error detection and correction of such operations have become an important issue recently. In most of the work reported so far, error detection and correction are applied using redundancies in space (hardware), time, and/or information (coding theory). In this work, schemes based on these redundancies are presented to detect errors in important finite field arithmetic operations resulting from hardware faults. Finite fields are used in a number of practical cryptosystems and channel encoders/decoders. The schemes presented here can detect errors in arithmetic operations of finite fields represented in different bases, including polynomial, dual and/or normal basis, and implemented in various architectures, including bit-serial, bit-parallel and/or systolic arrays.
Download or read book An Analysis of Error Detection Techniques for Arithmetic Logic Units written by Ryan Bickham and published by . This book was released on 2010 with total page 105 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book NASA Technical Paper written by and published by . This book was released on 1979 with total page 36 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book NASA Technical Paper written by United States. National Aeronautics and Space Administration and published by . This book was released on 1979 with total page 630 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Proceedings written by Milos D. Ercegovac and published by . This book was released on 1989 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Resilient Computer System Design written by Victor Castano and published by Springer. This book was released on 2015-04-15 with total page 271 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents a paradigm for designing new generation resilient and evolving computer systems, including their key concepts, elements of supportive theory, methods of analysis and synthesis of ICT with new properties of evolving functioning, as well as implementation schemes and their prototyping. The book explains why new ICT applications require a complete redesign of computer systems to address challenges of extreme reliability, high performance, and power efficiency. The authors present a comprehensive treatment for designing the next generation of computers, especially addressing safety critical, autonomous, real time, military, banking, and wearable health care systems.
Download or read book Proceedings of the IEEE International Conference on Electronics Circuits and Systems written by and published by . This book was released on 1996 with total page 666 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Defect and Fault Tolerance in VLSI Systems written by Israel Koren and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 362 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.
Download or read book Iaeng Transactions on Electrical Engineering written by Sio-Iong Ao and published by World Scientific. This book was released on 2012-10-31 with total page 325 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume contains revised and extended research articles written by prominent researchers. Topics covered include electrical engineering, circuits, artificial intelligence, data mining, imaging engineering, bioinformatics, internet computing, software engineering, and industrial applications. The book offers tremendous state-of-the-art advances in electrical engineering and also serves as an excellent reference work for researchers and graduate students working with/on electrical engineering.
Download or read book Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems written by Duncan Moore Henry Walker and published by Institute of Electrical & Electronics Engineers(IEEE). This book was released on 1992 with total page 360 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Application Specific Processors written by Earl E. Swartzlander Jr. and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt: Application Specific Processors is written for use by engineers who are developing specialized systems (application specific systems). Traditionally, most high performance signal processors have been realized with application specific processors. The explanation is that application specific processors can be tailored to exactly match the (usually very demanding) application requirements. The result is that no `processing power' is wasted for unnecessary capabilities and maximum performance is achieved. A disadvantage is that such processors have been expensive to design since each is a unique design that is customized to the specific application. In the last decade, computer-aided design systems have been developed to facilitate the development of application specific integrated circuits. The success of such ASIC CAD systems suggests that it should be possible to streamline the process of application specific processor design. Application Specific Processors consists of eight chapters which provide a mixture of techniques and examples that relate to application specific processing. The inclusion of techniques is expected to suggest additional research and to assist those who are faced with the requirement to implement efficient application specific processors. The examples illustrate the application of the concepts and demonstrate the efficiency that can be achieved via application specific processors. The chapters were written by members and former members of the application specific processing group at the University of Texas at Austin. The first five chapters relate to specific arithmetic which often is the key to achieving high performance in application specific processors. The next two chapters focus on signal processing systems, and the final chapter examines the interconnection of possibly disparate elements to create systems.
