Download or read book CMOS Test and Evaluation written by Manjul Bhushan and published by Springer. This book was released on 2014-12-03 with total page 431 pages. Available in PDF, EPUB and Kindle. Book excerpt: CMOS Test and Evaluation: A Physical Perspective is a single source for an integrated view of test and data analysis methodology for CMOS products, covering circuit sensitivities to MOSFET characteristics, impact of silicon technology process variability, applications of embedded test structures and sensors, product yield, and reliability over the lifetime of the product. This book also covers statistical data analysis and visualization techniques, test equipment and CMOS product specifications, and examines product behavior over its full voltage, temperature and frequency range.
Download or read book CMOS SOS Test Patterns for Process Evaluation and Control written by Loren W. Linholm and published by . This book was released on 1979 with total page 49 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Test Generation and Evaluation for Bridging Faults in CMOS VLSI Circuits written by Terry Ping-Chung Lee and published by . This book was released on 1995 with total page 196 pages. Available in PDF, EPUB and Kindle. Book excerpt: An efficient automatic test pattern generator for I$sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets. To accurately evaluate the test sets, fault grading is performed using a switch-level fault simulator and a mixed-mode electrical-level fault simulator. The test sets are compared with those generated by HITEC, a traditional gate-level test generator. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that for I$sb{DDQ}$ testing, the GA test sets outperform the HITEC test sets. When the test sets are truncated due to test time constraints, the fault coverages can differ by 10% or more. In addition to test generation and test evaluation, diagnosis (fault location) is also performed using both test sets. Diagnosis is performed using fault dictionaries constructed during test evaluation. In addition to the traditional full dictionary, two reduced dictionaries are also presented. The results show that the reduced dictionaries offer good size-resolution trade-offs when compared with the full dictionary.
Download or read book Evaluation of a CMOS SOS Process Using Process Validation Wafers written by John S. Suehle and published by . This book was released on 1982 with total page 42 pages. Available in PDF, EPUB and Kindle. Book excerpt: The objective of this work was to determine baseline electrical parameters that could be used to evaluate a fabrication process. Two lots of wafers containing NBS-16 test chips were fabricated at a commercial vendor in a radiation-hard, CMOS/SOS process. These wafers were then returned to NBS for testing and evaluation. Testing was performed using an automated computer-controlled integrated circuit test system. Test results were evaluated using analysis techniques which provided a statistical estimate of selected parameters and identified spatial correlations between data sets. Further analysis was then performed in order to identify process irregularities. A complete description of the test results and analysis procedure can be found in the appendices.
Download or read book Automatic Testing and Evaluation of Digital Integrated Circuits written by James T. Healy and published by . This book was released on 1981 with total page 264 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Testing and Reliable Design of CMOS Circuits written by Niraj K. Jha and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 239 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the last few years CMOS technology has become increas ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den sity and low power requirement. The ability to realize very com plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.
Download or read book A Process Development and Quality Evaluation Test Chip for Double level Metal CMOS written by George McCollough Ansel and published by . This book was released on 1983 with total page 460 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CMOS SOS Test Patterns for Process Evaluation and Control written by Loren W. Linholm and published by . This book was released on 1979 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CMOS Life Suitability Evaluation Program written by R. C. Maurer and published by . This book was released on 1979 with total page 355 pages. Available in PDF, EPUB and Kindle. Book excerpt: The results of a matrix of high-temperature accelerated life tests, 125C life tests, and 250 hour 250C lot acceptance tests were evaluated to determine the reliabiltiy of a cross-section of the complementary metal oxide semiconductor (CMOS) family of devices. The devices evaluated included a NOR gate, a flip-flop, a four bit adder, and a counter/divider. Each device was procured from two different manufacturers, and from three different lots of each manufacturer. The correlation of the Lot Acceptance data with the reliability of the devices revealed that the Class S Lot Acceptance Test, as specified in MIL-STD-883, Method 500.5 is approximately 50% effective screening for lot reliability. To minimize the possibility of rejecting good lots and/or accepting bad lots, two temperature Lot Acceptance Test is recommended. Using a two temperature Lot Acceptance Test at temperature above 200 C would permit control of both the activation energy and pre-exponential factor in the Arrhenius model. A 100% burn-9n is also recommended. Although burn-in would not improve all lots, it would improve the reliability of those lots which have a freak population with a high failure rate.
Download or read book Evaluation of Dynamic Current Testing for CMOS Domino Circuits written by Anis Musa Nazer and published by . This book was released on 2005 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: Transient current (iDDT) refers to the current drawn from the power supply durin g the transient switching of CMOS gates. Testing based on the transient current can detect many of the defects that can occur in ICs, such as resistive opens, w hich may not be detected by traditional voltage testing or by Leakage current (I DDQ) testing methods. A major set back for IDDQ testing methods is the increased leakage currents in today's ICs. Thus iDDT based testing has been often investi gated as an alternative or supplement to (IDDQ) testing. Little work has focused on iDDT testing for domino circuits. In this thesis, we propose a method for testing domino CMOS circuits using the transient power supp ly current. The method is based on monitoring the peak value of the transient cu rrent. This peak varies considerably with process variations, so each process ha s different thresholds; this problem will be addressed by proposing a normalizat ion procedure that allows us to use a single threshold for all processes. We pre sent also a test vector generation algorithm for testing large domino circuits. We evaluate the effectiveness of this testing method by simulation on various do mino circuits of different sizes. We develop and implement a partitioning technique to improve the fault coverage of the test method when used with large circuits. The algorithm divides the circ uit into different clusters where each cluster is fed by a different power suppl y branch. We also provide an automation system to simplify the process of genera ting the simulation files, injecting the defects in the circuit, running the sim ulations, storing the simulations output, processing the output signals, and fin ally gathering and analyzing the results.
Download or read book CMOS SRAM Circuit Design and Parametric Test in Nano Scaled Technologies written by Andrei Pavlov and published by Springer Science & Business Media. This book was released on 2008-06-01 with total page 203 pages. Available in PDF, EPUB and Kindle. Book excerpt: The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
Download or read book Gamma Irradiation Testing of Electronic Devices and Evaluation of Irradiated CMOS Components on MOSIS Test Chips written by Alice Hsuanchen Wu and published by . This book was released on 1990 with total page 310 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Testing for Small Delay Defects in Nanoscale CMOS Integrated Circuits written by Sandeep K. Goel and published by CRC Press. This book was released on 2017-12-19 with total page 259 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
Download or read book Microelectronic Test Structures for CMOS Technology written by Manjul Bhushan and published by Springer Science & Business Media. This book was released on 2011-08-26 with total page 401 pages. Available in PDF, EPUB and Kindle. Book excerpt: Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance and characteristics of MOSFETs and other circuit elements. Detailed examples are presented throughout, many of which are equally applicable to other microelectronic technologies as well. The authors’ overarching goal is to provide students and technology practitioners alike a practical guide to the disciplined design and use of test structures that give unambiguous information on the parametrics and performance of digital CMOS technology.
Download or read book Technical Abstract Bulletin written by and published by . This book was released on 1978 with total page 258 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Annual Department of Defense Bibliography of Logistics Studies and Related Documents written by United States. Defense Logistics Studies Information Exchange and published by . This book was released on 1991 with total page 856 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1976 with total page 1042 pages. Available in PDF, EPUB and Kindle. Book excerpt:
