Download or read book Built In Test for VLSI written by Paul H. Bardell and published by Wiley-Interscience. This book was released on 1987-10-20 with total page 376 pages. Available in PDF, EPUB and Kindle. Book excerpt: This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.
Download or read book VLSI Test Principles and Architectures written by Laung-Terng Wang and published by Elsevier. This book was released on 2006-08-14 with total page 809 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Download or read book VLSI Fault Modeling and Testing Techniques written by George W. Zobrist and published by Praeger. This book was released on 1993 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt: VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
Download or read book Logic Testing and Design for Testability written by Hideo Fujiwara and published by MIT Press (MA). This book was released on 1985-06-01 with total page 298 pages. Available in PDF, EPUB and Kindle. Book excerpt: Today's computers must perform with increasing reliability, which in turn depends onthe problem of determining whether a circuit has been manufactured properly or behaves correctly.However, the greater circuit density of VLSI circuits and systems has made testing more difficultand costly. This book notes that one solution is to develop faster and more efficient algorithms togenerate test patterns or use design techniques to enhance testability - that is, "design fortestability." Design for testability techniques offer one approach toward alleviating this situationby adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Becausethe cost of hardware is decreasing as the cost of testing rises, there is now a growing interest inthese techniques for VLSI circuits.The first half of the book focuses on the problem of testing:test generation, fault simulation, and complexity of testing. The second half takes up the problemof design for testability: design techniques to minimize test application and/or test generationcost, scan design for sequential logic circuits, compact testing, built-in testing, and variousdesign techniques for testable systems.Hideo Fujiwara is an associate professor in the Department ofElectronics and Communication, Meiji University. Logic Testing and Design for Testability isincluded in the Computer Systems Series, edited by Herb Schwetman.
Download or read book Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits written by M. Bushnell and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 690 pages. Available in PDF, EPUB and Kindle. Book excerpt: The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
Download or read book Built in Test Design for the Efficient Testing of VLSI Circuits written by Robert F. Molyneaux and published by . This book was released on 1990 with total page 136 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book On Line Testing for VLSI written by Michael Nicolaidis and published by Springer Science & Business Media. This book was released on 2013-03-09 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt: Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.
Download or read book An Introduction to Logic Circuit Testing written by Parag K. Lala and published by Springer Nature. This book was released on 2022-06-01 with total page 99 pages. Available in PDF, EPUB and Kindle. Book excerpt: An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References
Download or read book IDDQ Testing of VLSI Circuits written by Ravi K. Gulati and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 121 pages. Available in PDF, EPUB and Kindle. Book excerpt: Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Download or read book A Designer s Guide to Built In Self Test written by Charles E. Stroud and published by Springer Science & Business Media. This book was released on 2005-12-27 with total page 338 pages. Available in PDF, EPUB and Kindle. Book excerpt: A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.
Download or read book System on Chip Test Architectures written by Laung-Terng Wang and published by Morgan Kaufmann. This book was released on 2010-07-28 with total page 893 pages. Available in PDF, EPUB and Kindle. Book excerpt: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.
Download or read book Built in Self Test and Digital Self Calibration for RF SoCs written by Sleiman Bou-Sleiman and published by Springer Science & Business Media. This book was released on 2011-09-23 with total page 106 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book will introduce design methodologies, known as Built-in-Self-Test (BiST) and Built-in-Self-Calibration (BiSC), which enhance the robustness of radio frequency (RF) and millimeter wave (mmWave) integrated circuits (ICs). These circuits are used in current and emerging communication, computing, multimedia and biomedical products and microchips. The design methodologies presented will result in enhancing the yield (percentage of working chips in a high volume run) of RF and mmWave ICs which will enable successful manufacturing of such microchips in high volume.
Download or read book State of the Art Assessment of Testing and Testability of Custom LSI VLSI Circuits Volume VII Built In Testing BIT and Built In Test Equipment BITE written by Al J. Carlan and published by . This book was released on 1982 with total page 42 pages. Available in PDF, EPUB and Kindle. Book excerpt: Concurrent testing and nonconcurrent testing are the two major BIT techniques employed in VSLI circuit design; concurrent testing and nonconcurrent testing. concurrent testing allows circuit checkout during normal system; and may employ error detecting codes, self checking circuits, replication or electrical monitoring. Nonconcurrent testing requires a special test mode during which normal system operation is halted. Circuits must be added to generate the test patterns used during test mode. Circuits must be added to generate the test patterns used during test mode. Nonconcurrent testing is initiated by hardware implemented BITE or diagnostic software. (Author).
Download or read book VLSI Testing written by T. W. Williams and published by North Holland. This book was released on 1986 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers the spectrum of the testing problem. Areas covered include fault modeling, test generation, fault simulation, memory testing, design for testability, testability measures, PLA testing, and test equipment. The use of this volume will provide a good insight into the VLSI challenges in the area of testing - an area that has become increasingly important due to the emphasis on quality of VLSI products, and the associated costs. As a result, there has been a rapid expansion in the technologies associated with testing, and it is this technological growth which is reflected in the contributions to this volume.
Download or read book Self testing VLSI Design written by Vi︠a︡cheslav Nikolaevich I︠A︡rmolik and published by Elsevier Publishing Company. This book was released on 1993 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt: A distinctive feature of modern computer equipment development is the continuous increase in functionality and complexity of computer components. As a result of these advances, very large-scale integration (VLSI) circuits have found extensive application in the manufacture of computer products, personal computers included. Among a variety of recently evolved VLSI design technologies, the self-test VLSI design has gained particular prominence. design. A summary is given on self-test VLSI design results that have been obtained by scientists in leading scientific centres for computer integrated circuits. Emphasis is placed on the theoretical fundamentals of designing self-test VLSI building blocks, such as built-in test generators and output response analyzers. Particular attention is paid to: structural design of self-test VLSI circuits; design of universal modules for self-test VLSI circuits; and examination of the VLSI circuits for signature testability. It has been demonstrated that the design-for-testability techniques employed by this method provide ideal conditions for the straightforward implementation of self-test concepts. The work should prove useful for all those interested in both the basic facts and current research in this field.
Download or read book Advanced Simulation and Test Methodologies for VLSI Design written by G. Russell and published by Springer Science & Business Media. This book was released on 1989-02-28 with total page 406 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book An Introduction to Logic Circuit Testing written by Parag K. Lala and published by Morgan & Claypool Publishers. This book was released on 2009 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References
