Download or read book Automatic Test Pattern Generation for Analog Circuits written by Mark Joseph Marlett and published by . This book was released on 1991 with total page 80 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book 1983 IEEE ATPG Workshop Proceedings written by and published by . This book was released on 1983 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Test Pattern Generation using Boolean Proof Engines written by Rolf Drechsler and published by Springer Science & Business Media. This book was released on 2009-04-22 with total page 196 pages. Available in PDF, EPUB and Kindle. Book excerpt: In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.

Download or read book Analog and Mixed signal Test written by Bapiraju Vinnakota and published by . This book was released on 1998 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: More and more chips are being designed with both analog and digital circuitry next to each other, which makes testing analog circuitry even more challenging. This comprehensive guide reviews all the potential testing options, helping designers, engineers, CAD developers, and researchers choose the most cost-effective, accurate solutions for both mixed-signal and analog-only testing.

Download or read book Modeling the Difficulty of Automatic Test Pattern Generation for Sequential Circuits written by Thomas E. Marchok and published by . This book was released on 1995 with total page 138 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Several manufacturing challenges have accompanied the explosive growth in the scale of integration for VLSI circuits. One of these is the increased difficulty of generating manufacturing test sets, which has resulted from the vast increase in the ratio of the number of transistors to the number of I/O pins. The difficulty of test generation is crucial since it impacts both the resultant product quality and time to market, both of which continue to gain importance in the present day semiconductor industry. Design for testability (DFT) techniques can be used to offset this difficulty. The mechanics of such techniques are well understood. DFT techniques are also known to increase other manufacturing costs and to decrease performance. Thus the relevant issue facing designers is not how to use DFT, but rather if such techniques should be applied. The correct decision is a matter of economics. Integrated circuit (IC) designers must balance manufacturing costs, performance, time to market, and product quality concerns. Achieving the desired balance requires the ability to quantify trade-offs in the different manufacturing costs which various DFT techniques would affect. Unfortunately, test generation cost is among the least predictable of these affected costs, even though the principal reason that DFT techniques are often applied is to reduce the difficulty of test generation. Furthermore, there does not exist a complete understanding of which circuit attributes influence the difficulty of test generation. In this thesis, a model is developed which predicts the difficulty of automatic test generation for non-scan sequential circuits. This model is based on a newly recognized circuit attribute, termed density of encoding, which differs from those notions which have been used to describe this difficulty in the past. This thesis also discusses how the concept of the density of encoding can be applied to devise more powerful sequential automatic test pattern generation algorithms, more efficient DFT techniques, and more effective synthesis for testability schemes."

Download or read book Testing and Diagnosis of Analog Circuits and Systems written by Ruey-wen Liu and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 290 pages. Available in PDF, EPUB and Kindle. Book excerpt: IS THE TOPIC ANALOG TESTING AND DIAGNOSIS TIMELY? Yes, indeed it is. Testing and Diagnosis is an important topic and fulfills a vital need for the electronic industry. The testing and diagnosis of digital electronic circuits has been successfuIly developed to the point that it can be automated. Unfortu nately, its development for analog electronic circuits is still in its Stone Age. The engineer's intuition is still the most powerful tool used in the industry! There are two reasons for this. One is that there has been no pressing need from the industry. Analog circuits are usuaIly small in size. Sometimes, the engineer's experience and intuition are sufficient to fulfill the need. The other reason is that there are no breakthrough results from academic re search to provide the industry with critical ideas to develop tools. This is not because of a lack of effort. Both academic and industrial research groups have made major efforts to look into this problem. Unfortunately, the prob lem for analog circuits is fundamentally different from and much more diffi cult than its counterpart for digital circuits. These efforts have led to some important findings, but are still not at the point of being practicaIly useful. However, these situations are now changing. The current trend for the design of VLSI chips is to use analog/digital hybrid circuits, instead of digital circuits from the past. Therefore, even Ix x Preface though the analog circuit may be small, the total circuit under testing is large.

Download or read book Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits written by M. Bushnell and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 690 pages. Available in PDF, EPUB and Kindle. Book excerpt: The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.

Download or read book Automatic Test Pattern Generation for Three state Circuits written by Johannes Theodorus van der Linden and published by . This book was released on 1996 with total page 221 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Automatic Test Pattern Generation Techniques for Built in Self test of Digital Circuits written by Dimitrios N. Kagaris and published by . This book was released on 1994 with total page 408 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book At speed Scan Insertion and Automatic Test Pattern Generation of Integrated Circuits with Fault grading and Speed grading written by Joseph Fang and published by . This book was released on 2005 with total page 120 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the growing complexity of today's integrated circuit designs, engineers have abandoned the use of pure functional test vectors wherever possible, and adopted various DFT solutions to make their designs more test-friendly. The most common DFT approach for digital designs is scan insertion and automatic test pattern generation (ATPG). ATPG is performed based on fault models associated with the design or gates within the design. Traditionally, the most popular model is the stuck-at model. However, as transistor size continues to shrink, new defect mechanisms start to appear that affect the speed of the design, and so can no longer be properly modelled by this model. Consequently, a new fault model called transition-delay fault models is created to allow ATPG to detect at-speed defects. Another model called path-delay fault model is also created for speed-grading/binning and I/0 timing characterization on scan-inserted designs. As part of an ongoing DFT development for PMC-Sierra Inc., a suite of automation flows have been implemented to perform AC-Scan ATPG. This includes transition-delay ATPG with DC top-up ATPG for delay defect detection, path-delay ATPG for speed-grading/binning and I/0 timing characterization, and AC-scan ATPG for RAM interfaces with multi-load algorithm.

Download or read book A topological search algorithm for improved automatic test pattern generation on digital circuits written by Thomas Edward Kirkland and published by . This book was released on 1986 with total page 274 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Study of Automatic Test Pattern Generation Systems written by Kyuchull Kim and published by . This book was released on 1992 with total page 348 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Deterministic Automatic Test Pattern Generation for Built in Self Test System written by Muhammad Nazir Mohammed Khalid and published by . This book was released on 2006 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt: With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly designed with Built-In Self Test facility. For this reason, development of test pattern for BIST based on combination of Linear Feedback Shift Register (LFSR) and deterministic ATPG (DATPG) approach could provide more solutions, such as reduce testing time, high fault coverage and low area overhead. One of the key challenges in BIST is the design of the Test Pattern Generation (TPG) that promised high fault coverage. The test pattern generation can be generated either manually or automatically. Problems related to ATPG are linked to the controllability and observability of the nodes in circuits. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational circuit. To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. Altera Max+plus II software is used to simulate the DATPG design to achieve the minimum test patterns for digital combinational circuit. The simulation result will be presented in the form of waveform. The results of DATPG for digital combinational circuit show that the sequence of LFSR has been reduced significantly. In BIST application, the minimum test patterns are applied to the adder/substractor (A/S) known as circuit under test (CUT). A parallel A/S is chosen as a CUT due to the simplicity of the circuit architecture. The A/S is used to verify the proposed DATPG performance. Only one basic cell of the parallel A/S is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both A/S inputs simultaneously. By reducing the number of test pattern, the testing time to market and manufacturing time is expected to reduce leading to reduction in the product cost.

Download or read book Modeling the Difficulty of Sequential Automatic Test Pattern Generation written by Thomas E. Marchok and published by . This book was released on 1995 with total page 22 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses the core issue involved in IC design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques."

Download or read book Time Efficient Automatic Test Pattern Generation Systems written by Byungse So and published by . This book was released on 1994 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Test Frequency Selection for Analog Circuits Based on Bode Diagrams and Equivalent Fault Grouping written by and published by . This book was released on 2004 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Attempts have been made in the analog circuit ATPG area especially in the past ten years and have met some degree of success. But, there is still no widely accepted ATPG technique for analog circuit test so far. In this thesis, we review recent developments in this area and then present a novel test frequency selection technique for frequency-based analog circuit testing. The proposed method is based on the symbolic transfer function of the circuit under test, and estimates the good and faulty circuit responses by asymptotic approximation for the Bode diagrams of both good and faulty circuit transfer functions. Then, we search a frequency to maximize the fault effect using a simple maximum-value-search algorithm for a set of straight lines, instead of searching the entire frequency range to find a maximum value of a non-linear function. This drastically reduces the computation complexity. An equivalent fault grouping method is also proposed to classify a list of faults into equivalent groups by pure symbolic and partial symbolic transfer function analyses before test generation. Hence, test generation is only necessary to be performed on one representative fault from each equivalent group, instead of all, without changing the fault coverage. Integrate both techniques with a test set compaction technique, a complete and efficient ATPG system can thus be developed. The ultimate test patterns generated are also applicable to analog built-in self-test, when combined with limited amount of hardware.

Download or read book Mixed Signal Built In Self Test for Analog Circuits written by Charles E. Stroud and published by . This book was released on 1999 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: A Built-In Self-Test architecture was developed for testing analog circuits in mixed-signal systems. The Built-In Self-Test circuitry primarily resides in the digital portion of the mixed-signal system in order to minimize performance impact on the analog circuitry. The test pattern generation portion of the Built-In Self-Test circuitry produces a number of different test waveforms found to be effective in detecting faults in the analog circuitry. The output response analysis function consists of a double-precision accumulator that facilitates determination of the faulty/fault-free status of an analog circuit with acceptable component parameter variations. Ten benchmark circuits were established for the evaluation of analog testing approaches along with acceptable component parameter variations and a standard set of faults and fault models for each benchmark circuit. Finally, an equation was developed for the calculation of analog fault coverage that takes into consideration the probability of potential detection of faults due to component parameter variation. Evaluation of the Built-In Self-Test architecture via analog fault simulation using the benchmark circuits and the fault coverage equation indicates that the approach is effective in detecting catastrophe and parametric faults in a wide variety of analog circuits.