Download or read book Area efficient Stochastic Decoder Architectures for Non binary LDPC Codes written by and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Efficient VLSI Architectures for Non binary Low Density Parity Check Decoding written by Fang Cai and published by . This book was released on 2011 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt: Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this thesis, two VLSI designs for NB-LDPC decoders based on two novel check node processing schemes are proposed. The first design is based on forward-backward check node processing. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm less than q messages are kept on each edge of the associated Tanner graph. The computation units and the scheduling of the computations are optimized in the context of layered decoding to reduce the area requirement and increase the speed. This thesis also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity and latency analysis, our design is much more efficient than any previous design. Our proposed decoder for a (744, 653) code over GF(32) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out. The second design is based on a proposed trellis based check node processing scheme. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as 'compressed' c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code over GF(32) can achieve the same throughput with only 46% of the area.

Download or read book An Efficient Decoder Architecture for Non binary LDPC Codes in High Order Fields written by Wei-Xiang Chu and published by . This book was released on 2020 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Low complexity Decoding Algorithms and Architectures for Non binary LDPC Codes written by Fang Cai and published by . This book was released on 2013 with total page 149 pages. Available in PDF, EPUB and Kindle. Book excerpt: Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this thesis, three decoding algorithms and corresponding VLSI architectures are proposed for NB-LDPC codes to lower the computational complexity and memory requirement. The first design is based on the proposed relaxed Min-max decoding algorithm. A novel relaxed check node processing scheme is proposed for the Min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p̂) can be uniquely represented by a linear combination of $p$ independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25̂) can achieve 52% higher efficiency in terms of throughput-over-area ratio. The second design is based on a proposed enhanced iterative hard reliability-based majority-logic decoding. The recently developed iterative hard reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. Novel schemes are proposed for the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E- )IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss. The third design is based on a proposed check node decoding scheme using power representation of finite field elements. Novel schemes are proposed for the Min-max check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs based on the Min-max algorithm with forward-backward scheme, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over GF(32), the proposed scheme reduces the CNU area by at least 32%, and leads to higher clock frequency.

Download or read book Stochastic Decoding of LDPC Codes Over GF q written by Gabi Sarkis and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Decoder Architectures and Implementations for Quasi cyclic Low density Parity check Codes written by Xiaoheng Chen and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Since the rediscovery of low-density parity-check (LDPC) codes in the late 1990s, tremendous progress has been made in code construction and design, decoding algorithms, and decoder implementation of these capacity-approaching codes. Recently, LDPC codes are considered for applications such as high-speed satellite and optical communications, the hard disk drives, and high-density flash memory based storage systems, which require that the codes are free of error-floor down to bit error rate (BER) as low as 10−12 to 10−15. FPGAs are usually used to evaluate the error performance of codes, since one can exploit the finite word length and extremely high internal memory bandwidth of an FPGA. Existing FPGA-based LDPC decoders fail to utilize the configurability and read-first mode of embedded memory in the FPGAs, and thus result in limited throughput and codes sizes. Four optimization techniques, i.e., vectorization, folding, message relocation, and circulant permutation matrix (CPM) sharing, are proposed to improve the throughput, scalability, and efficiency of FPGA-based decoders. Also, a semi-automatic CAD tool called QCSYN (Quasi-Cyclic LDPC decoder SYNthesis) is designed to shorten the implementation time of decoders. Using the above techniques, a high-rate (16129,15372) code is shown to have no error-floor down to the BER of 10−14. Also, it is very difficult to construct codes that do not exhibit an error floor down to 10−15 or so. Without detailed knowledge of dominant trapping sets, a backtracking-based reconfigurable decoder is designed to lower the error floor of a family of structurally compatible quasi-cyclic LDPC codes by one to two orders of magnitudes. Hardware reconfigurability is another significant feature of LDPC decoders. A tri-mode decoder for the (4095,3367) Euclidean geometry code is designed to work with three compatible binary message passing decoding algorithms. Note that this code contains 262080 edges (21.3 times of the (2048,1723) 10GBASE-T code) in its Tanner graph and is the largest code ever implemented. Besides, an efficient QC-LDPC Shift Network (QSN) is proposed to reduce the interconnect delay and control logic of circular shift network, a core component in the reconfigurable decoder that supports a family of structurally compatible codes. The interconnect delay and control logic area are reduced by a factor of 2.12 and 8, respectively. Non-binary LDPC codes are effective in combating burst errors. Using the power representation of the elements in the Galois field to organize both intrinsic and extrinsic messages, we present an efficient decoder architecture for non-binary QC-LDPC codes. The proposed decoder is reconfigurable and can be used to decode any code of a given field size. The decoder supports both regular and irregular non-binary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.

Download or read book High Performance and Energy Efficient Decoder Design for Non Binary LDPC Codes written by Yuta Toriyama and published by . This book was released on 2016 with total page 133 pages. Available in PDF, EPUB and Kindle. Book excerpt: Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts. Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency. We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.

Download or read book Stochastic Decoding of Low Density Parity check Codes written by Saeed Sharifi Tehrani and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Adaptive Multiset Stochastic Decoding of Non binary LDPC Codes written by Alexandru Ciobanu and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: In this thesis, we propose a new stochastic decoding algorithm for non-binary LDPC codes with d_v = 2, which is based on the concept of a mutliset, a generalization of the set that allows for multiple occurrences of the same element. The algorithm is called Adaptive Multiset Stochastic Algorithm (AMSA) and represents probability mass functions as multisets, which simplifies the structure of the variable node. AMSA reduces the run-time complexity of one decoding cycle to O(q) for regular memory architectures, and to O(1) if a custom SRAM architecture is used. Two fully-parallel AMSA decoders are implemented on FPGA for two versions of a (192,96) (2,4)-regular code, one over GF(64) and the other over GF(256), both achieving a maximum clock frequency of 108 MHz and a throughput of 65 Mbit/s at E_b/N_0 = 2.4 dB. We also propose an SRAM architecture for ASIC implementations that reduces the run-time complexity of a decoding cycle to O(1) and achieves a throughput of 6...

Download or read book Efficient Algorithms for Stochastic Decoding of LDPC Codes written by Kuo-Lun Huang and published by . This book was released on 2016 with total page 125 pages. Available in PDF, EPUB and Kindle. Book excerpt: The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models. We statistically analyze the behavior of stochastic LDPC decoding, including randomization in the stochastic streams and convergence of transition probabilities in iterative decoding process. We also present a space and time-efficient code bit determination method for stochastic LDPC decoders. In addition, we investigate and characterize the decoding errors of stochastic LDPC decoders and as an example, study the stochastic-decoding-specific trapping sets in the (1056,528) LDPC code used in the WiMAX standard. This study helps to develop methods to lower the error floor of stochastic decoding. We propose a reduced-latency stochastic decoding algorithm for LDPC codes. The proposed algorithm, called Conditional Stochastic Decoding (CSD), improves error rate performance and reduces the decoding latency by more than 30% compared with the existing stochastic decoders. We also characterize the performance of CSD in various communication schemes. For example, we show the advantages of using the proposed CSD algorithm in the Automatic Repeat reQuest (ARQ) scheme when compared with other iterative decoding algorithms. We extend our study of stochastic decoding to non-AWGN channel models including the Binary Symmetric Channel (BSC), the Z-channel, and the Rayleigh fading channel. We introduce scaling methods to improve the performance of stochastic decoding on these channel models. On the Rayleigh fading channel, the proposed method not only reduces the computational complexity of the stochastic decoding, but also provides 3-dB improvement in performance and lowers the error floor. Simplicity of hardware implementation, low latency, and good error rate performance of the proposed schemes make them suitable for emerging communication standards.

Download or read book Advanced Hardware Design for Error Correcting Codes written by Cyrille Chavet and published by Springer. This book was released on 2014-10-30 with total page 197 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.

Download or read book Channel Coding Theory Algorithms and Applications written by and published by Academic Press. This book was released on 2014-07-29 with total page 687 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book gives a review of the principles, methods and techniques of important and emerging research topics and technologies in Channel Coding, including theory, algorithms, and applications. Edited by leading people in the field who, through their reputation, have been able to commission experts to write on a particular topic. With this reference source you will: - Quickly grasp a new area of research - Understand the underlying principles of a topic and its applications - Ascertain how a topic relates to other areas and learn of the research issues yet to be resolved - Quick tutorial reviews of important and emerging topics of research in Channel Coding - Presents core principles in Channel Coding theory and shows their applications - Reference content on core principles, technologies, algorithms and applications - Comprehensive references to journal articles and other literature on which to build further, more specific and detailed knowledge

Download or read book High Performance Decoder Architectures For Low Density Parity Check Codes written by Kai Zhang and published by . This book was released on 2012 with total page 244 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted to exploring efficient VLSI architectures for high-performance LDPC decoders and LDPC-like detectors in sparse inter-symbol interference (ISI) channels. The performance of an LDPC decoder is mainly evaluated by area efficiency, error-correcting capability, throughput and rate flexibility. With this work we investigate tradeoffs between the four performance aspects and develop several decoder architectures to improve one or several performance aspects while maintaining acceptable values for other aspects ... Layered decoding algorithm, which is popular in LDPC decoding, is also adopted in this paper. Simulation results show that the layered decoding doubles the convergence speed of the iterative belief propagation process. Exploring the special structure of the connections between the check nodes and the variable nodes on the factor graph, we propose an effective detector architecture for generic sparse ISI channels to facilitate the practical application of the proposed detection algorithm. The proposed architecture is also reconfigurable in order to switch flexible connections on the factor graph in the time-varying ISI channels.

Download or read book Algebraic Constructions of High Performance and Efficiently Encodable Non binary Quasi cyclic LDPC Codes written by Bo Zhou and published by . This book was released on 2008 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book An Area Efficient Architecture for the Implementation of LDPC Decoder written by Lan Yang and published by . This book was released on 2011 with total page 52 pages. Available in PDF, EPUB and Kindle. Book excerpt: Due to its near Shannon limit performance in high speed communication, low-density parity check (LDPC) code has performed a strong comeback recent years. In this work, a partial parallel decoding architecture is proposed based on a column-layered LDPC decoding scheme [2]. The purpose of this work is to make a tradeoff between area cost and throughput. I construct the structure of the partial parallel decoder, and compare its throughput and area cost with the design in [2]. Then I obtain the synthesis results of my design with Xilinx FPGA tool. The device utilization summary and timing summary are provided at the end of this work. Comparing with the design in [2], the partial parallel design in my work needs much less hardware resources. As a result, when the area is limit and a lower throughput is acceptable, my design can be considered instead of the design in [2].

Download or read book Non binary Protograph based LDPC Codes written by Yizeng Sun and published by . This book was released on 2013 with total page 40 pages. Available in PDF, EPUB and Kindle. Book excerpt: Non-binary LDPC codes can outperform binary LDPC codes using sum-product algorithm with higher computation complexity. Non-binary LDPC codes based on protographs have the advantage of simple hardware architecture. In the first part of this thesis, we will use EXIT chart analysis to compute the thresholds of different protographs over GF(q). Based on threshold computation, some non-binary protograph-based LDPC codes are designed and their frame error rates are compared with binary LDPC codes. For maximum-likelihood decoder, weight enumerator can predict frame error rate of an LDPC code. In the second part of this thesis, we calculate weight enumerators of protograph-based non-binary LDPC code ensembles both for finite length case and asymptotic case. In addition, the trapping set and stopping set enumerators are presented.

Download or read book A Class of Non binary LDPC Codes written by Deepak Gilra and published by . This book was released on 2003 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: In this thesis we study Low Density Parity Check (LDPC) and LDPC like codes over non-binary fields. We extend the concepts used for non-binary LDPC codes to generalize Product Accumulate (PA) codes to non-binary fields. We present simulation results that show that PA codes over GF(4) performs considerably better than binary PA codes at smaller block lengths and slightly better at large block lengths. We also propose a trellis based decoding algorithm to decode PA codes and show that its complexity is considerably lower than the message-passing algorithm. In the second part of the thesis we study the convergence properties of non-binary PA codes and non-binary LDPC codes. We use EXIT-charts to study the convergence properties of non-binary LDPC codes with different mean column weights and show why certain irregularities are better. Although the convergence threshold predicted by EXIT-charts on non-binary LDPC codes is quite optimistic we can still use EXIT-charts for comparison between non-binary LDPC codes with different mean column weights.