Download or read book Architectural Techniques for Memory Oversight in Multiprocessors written by Arrvindh Shriraman and published by . This book was released on 2010 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Computer architects have exploited the transistors afforded by Moore's law to provide software developers with high performance computing resources. Software has translated this growth in hardware resources into improved features and applications. Unfortunately, applications have become increasingly complex and are prone to a variety of bugs when multiple software modules interact. The advent of multicore processors introduces a new challenge, parallel programming, which requires programmers to coordinate multiple tasks. This dissertation develops general-purpose hardware mechanisms that address the dual challenges of parallel programming and software reliability. We have devised hardware mechanisms in the memory hierarchy that shed light on the memory system and control the visibility of data among the multiple threads. The key novelty is the use of cache coherence protocols to implement hardware mechanisms that enable software to track and regulate memory accesses at cache-line granularity. We demonstrate that exposing the events in the memory hierarchy provides useful information that was either previously invisible to software or would have required heavyweight instrumentation. Focusing on the challenge of parallel programming, our mechanisms aid implementations of Transactional Memory (TM), a programming construct that seeks to simplify synchronization of shared state. We develop two mechanisms, Alert-On-Update (AOU) and Programmable Data Isolation (PDI), to accelerate common TM tasks. AOU selectively exposes cache events, including those that are triggered by remote accesses, to software in the form of events. TM runtimes use it to detect accesses that overlap between transactions (i.e., conflicts), and track a transaction's status. Programmable-Data-Isolation (PDI) allows multiple threads to temporarily hide their speculative writes from concurrent threads in their private caches until software decides to make them visible. We have used PDI and AOU to implement two TM run-time systems, RTM and FlexTM. Both RTM and FlexTM are flexible runtimes that permit software control of the timing of conflict resolution and the policy used for conflict management. To address the challenge of software reliability, we propose Sentry, a lightweight, flexible access-control mechanism. Sentry allows software to regulate the reads and writes to memory regions at cache-line granularity based on the context in the program. Sentry coordinates the coherence states in a novel manner to eliminate the need for permission checks entirely for a large majority of the program's accesses (all cache hits), thereby improving efficiency. Sentry improves application reliability by regulating data visibility and movement among the multiple software modules present in the application. We use a real-world webserver, Apache, as a case study to illustrate Sentry's ability to guard the core application from vulnerabilities in the application's modules."--Leaves vii-viii

Download or read book Architectural Features for Scalable Shared Memory Multiprocessors written by Joonwon Lee and published by . This book was released on 1991 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Architectural Techniques to Enable Reliable and High Performance Memory Hierarchy in Chip Multi processors written by Amin Jadidi and published by . This book was released on 2018 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Constant technology scaling has enabled modern computing systems to achieve high degrees of thread-level parallelism, making the design of a highly scalable and dense memory hierarchy a major challenge. During the past few decades SRAM has been widely used as the dominant technology to build on-chip cache hierarchies. On the other hand, for the main memory, DRAM has been exploited to satisfy the applications demand. However, both of these two technologies face serious scalability and power consumption problems. While there has been enormous research work to address the drawbacks of these technologies, researchers have also been considering non-volatile memory technologies to replace SRAM and DRAM in future processors. Among dierent non-volatile technologies, Spin-Transfer Torque RAM (STT-RAM) and Phase Change Memory (PCM) are the most promising candidates to replace SRAM and DRAM technologies, respectively. Researchers believe that the memory hierarchy in future computing systems will consist of a hybrid combination of current technologies (i.e., SRAM and DRAM) and non-volatile technologies (e.g., STT-RAM, and PCM). While each of these technologies have their own unique features, they have some specic limitations as well. Therefore, in order to achieve a memory hierarchy that satises all the system-level requirements, we need to study each of these memory technologies.In this dissertation, the author proposes several mechanisms to address some of the major issues with each of these technologies. To relieve the wear-out problem in a PCM-based main memory, a compression-based platform is proposed, where the compression scheme collaborates with wear-leveling and error correction schemes to further extend the memory lifetime. On the other hand, to mitigate the write disturbance problem in PCM, a new write strategy as well as a non-overlapping data layout is proposed to manage the thermal disturbance among adjacent cells.For the on-chip cache, however, we would like to achieve a scalable low-latency conguration. To this end, the author proposes a morphable SLC-MLC STT-RAM cache which dynamically trade-os between larger capacity and lower latency, based on the applications demand. While adopting scalable memory technologies, such as STT-RAM, improves the performance of cache-sensitive applications, the cache thrashing problem will stil exist in applications with very large data working-set. To address this issue, the author proposes a selective caching mechanism for highly parallel architectures. And, also introduces a criticality-aware compressed last-level cache which is capable of holding a larger portion of the data working-set while the access latency is kept low.

Download or read book Parallel Architectural Simulations on Shared memory Multiprocessors written by Pavlos Konas and published by . This book was released on 1994 with total page 506 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ever increasing size and complexity of computer systems made possible by the rapid advances in VLSI technology and computer architecture, have resulted in simulations which require excessive amounts of processing power and memory. One way to meet these requirements of detailed computer simulations is to execute them on multiprocessors. This dissertation focuses on the development of a parallel method for the fast and efficient execution of architectural simulations on shared-memory multiprocessors. We identify five issues which are important to the performance of a parallel simulator, and we address each of them separately as well as in coordination with one another. First, we study the behavior and examine the parallelism available in architectural and logic-level simulations. The results of our study show that such designs do contain significant inherent parallelism. However, for a synchronous method to be efficient in their simulations it needs to exploit the clock effect and to handle well the simulation steps with limited parallelism. In addition, traces of parallelism are shown to be important in describing the dynamic behavior of the simulation parallelism, and in identifying the limitations of parallel simulation methods. Second, we present a synchronous parallel simulation method (SPaDES) which improves upon existing synchronous methods in many ways, and performs well on both centralized memory and on NUMA multiprocessors. We also present AdvanCE SPaDES, in which an aggressive mechanism is combined with a nonblocking barrier to facilitate the extraction and exploitation of parallelism in situations where the simulation does not contain enough inherent parallelism for the processors to exploit. AdvanCE SPaDES improves the performance of the parallel simulator, especially when the original method may not perform so well. Third, we present sensitive partitioning, a method which accounts for the synchronous nature of a SPaDES simulator, as well as for characteristics of architectural and logic-level designs. Using several metrics we compare the performance of sensitive partitioning to other widely used partitioning methods in the parallel simulation of logic-level designs. The results of our study show that sensitive partitioning performs well in the partitioning of the examined designs, and that its performance can be further improved by utilizing more accurate estimations of the design characteristics. Fourth, we present a novel approach to processor self-scheduling which accounts for characteristics of the simulation method and of the target simulation area. The presented approach combines the advantages of an efficient data structure with inexpensive and easily accessible affinity information to achieve an efficient parallel execution. A study of the presented approach shows that it provides better performance than simpler approaches which utilize less affinity information. Finally, we discuss the importance of an optimizing compiler in improving the efficiency of a parallel simulator. We argue that information available to the compiler during the analysis of the simulated system can significantly improve the efficiency of the parallel simulator, and we present optimizations which are important in SPaDES simulations.

Download or read book Architectural Support for Scalable Speculative Parallelization in Shared memory Multiprocessors written by Marcelo Hehl Cintra and published by . This book was released on 2001 with total page 216 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Defense Department Authorization and Oversight Research development test and evaluation written by United States. Congress. House. Committee on Armed Services and published by . This book was released on 1983 with total page 1414 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Defense Department Authorization and Oversight Research development test and evaluation April 12 18 19 20 22 25 26 27 and 28 1983 written by United States. Congress. House. Committee on Armed Services and published by . This book was released on 1983 with total page 1404 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Computer Organization and Design RISC V Edition written by David A. Patterson and published by Morgan Kaufmann. This book was released on 2017-05-12 with total page 700 pages. Available in PDF, EPUB and Kindle. Book excerpt: The new RISC-V Edition of Computer Organization and Design features the RISC-V open source instruction set architecture, the first open source architecture designed to be used in modern computing environments such as cloud computing, mobile devices, and other embedded systems. With the post-PC era now upon us, Computer Organization and Design moves forward to explore this generational change with examples, exercises, and material highlighting the emergence of mobile computing and the Cloud. Updated content featuring tablet computers, Cloud infrastructure, and the x86 (cloud computing) and ARM (mobile computing devices) architectures is included. An online companion Web site provides advanced content for further study, appendices, glossary, references, and recommended reading. Features RISC-V, the first such architecture designed to be used in modern computing environments, such as cloud computing, mobile devices, and other embedded systems Includes relevant examples, exercises, and material highlighting the emergence of mobile computing and the cloud

Download or read book A Primer on Memory Consistency and Cache Coherence written by Vijay Nagarajan and published by Morgan & Claypool Publishers. This book was released on 2020-02-04 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Download or read book Scientific and Technical Aerospace Reports written by and published by . This book was released on 1995 with total page 456 pages. Available in PDF, EPUB and Kindle. Book excerpt: Lists citations with abstracts for aerospace related reports obtained from world wide sources and announces documents that have recently been entered into the NASA Scientific and Technical Information Database.

Download or read book Computer Organization and Design written by John L. Hennessy and published by . This book was released on 2000 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book NASA SP 7500 written by United States. National Aeronautics and Space Administration and published by . This book was released on with total page 598 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Digital Integrated Circuit Design written by Hubert Kaeslin and published by Cambridge University Press. This book was released on 2008-04-28 with total page 878 pages. Available in PDF, EPUB and Kindle. Book excerpt: This practical, tool-independent guide to designing digital circuits takes a unique, top-down approach, reflecting the nature of the design process in industry. Starting with architecture design, the book comprehensively explains the why and how of digital circuit design, using the physics designers need to know, and no more.

Download or read book Under the Hood of Net Memory Management written by Chris Farrell and published by Red Gate Books. This book was released on 2011 with total page 238 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book starts with an introduction to the core concepts of .NET memory management and garbage collection, and then quickly layers on additional details and intricacies. Once you're up to speed, you can dive into the guided troubleshooting tour, and tips for engineering your application to maximise performance. And to finish off, take a look at some more sophisticated considerations, and even a peek inside the Windows memory model.

Download or read book Management written by and published by . This book was released on 1992 with total page 180 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Soft Architecture Machines written by Nicholas Negroponte and published by MIT Press (MA). This book was released on 1975 with total page 264 pages. Available in PDF, EPUB and Kindle. Book excerpt: A utopian view of the future relationship between architects and machines.

Download or read book The Linux Kernel Primer written by Claudia Salzberg Rodriguez and published by Prentice-Hall PTR. This book was released on 2006 with total page 656 pages. Available in PDF, EPUB and Kindle. Book excerpt: Offers a comprehensive view of the underpinnings of the Linux kernel on the Intel x86 and the Power PC.